77 portb(this,
"B", true, 6),
78 gtccr_reg(&coreTraceGroup,
"GTCCR"),
79 prescaler0(this,
"0", >ccr_reg, 0, 7),
80 premux0(&prescaler0,
PinAtPort(&portb, 2))
85 if(flash_bytes > 2U * 1024U)
93 if(ram_bytes > 128U) {
217 rw[0x27]= &ad->admux_reg;
218 rw[0x26]= &ad->adcsra_reg;
219 rw[0x25]= &ad->adch_reg;
220 rw[0x24]= &ad->adcl_reg;
221 rw[0x23]= &ad->adcsrb_reg;
Basic AVR device, contains the core functionality.
IOSpecialReg gtccr_reg
GTCCR IO register.
PrescalerMultiplexerExt premux0
prescaler multiplexer for timer 0
IOSpecialReg * mcucr_reg
MCUCR IO register.
OSCCALRegister * osccal_reg
OSCCAL IO register.
ADC reference is selected on 4 diff. sources: Vcc, aref pin, bandgap or 2.56V reference.
Implements a stack with stack register using RAM as stackarea.
IOReg< HWEeprom > eedr_reg
void registerIrq(int vector, int irqBit, ExternalIRQ *extirq)
Implement CLKPR register.
bool flagJMPInstructions
CALL and JMP instructions are available (only on devices with bigger flash)
Pin & GetPin(unsigned char pinNo)
returns a pin reference of pin with pin number
oscillator version 5.x, 8bit, two ranges
IOReg< HWAcomp > acsr_reg
ACSR IO register.
IOReg< HWTimer8 > tcnt_reg
counter register
GPIORegister * gpior2_reg
GPIOR2 Register.
A register in IO register space unrelated to any peripheral. "GPIORx" in datasheets.
TimerIRQRegister * timer01irq
timer interrupt unit for timer 0 and 1
Handler for external IRQ's to communicate with IRQ system and mask/flag registers.
Represents a timer interrupt line, Frontend for timer interrupts.
void SetFuseConfiguration(int size, unsigned long defvalue)
Configure fuses.
GPIORegister * gpior1_reg
GPIOR1 Register.
IOReg< HWTimer8_2C > tccrb_reg
control register B
IOSpecialReg tifr_reg
the TIFRx register
HWARef * aref
adc reference unit
IOReg< HWTimer8_2C > tccra_reg
control register A
IOSpecialReg * pllcsr_reg
PLLCSR IO register.
HWTimerTinyX5 * timer1
timer 1 unit
TraceValueCoreRegister coreTraceGroup
AVR device class for ATTiny45, see AvrDevice_attinyX5.
timer unit for timer 1 on ATtiny25/45/85
IOReg< HWTimerTinyX5 > tccr_reg
control register
bool flagMULInstructions
(F)MULxx instructions are available
IOReg< HWEeprom > eearh_reg
HWPort portb
port B (only 6 bit)
HWAcomp * acomp
analog compare unit
ExternalIRQHandler * extirq
external interrupt support
AvrDevice_attinyX5(unsigned ram_bytes, unsigned flash_bytes, unsigned ee_bytes)
AVR device class for ATTiny25, see AvrDevice_attinyX5.
Pin * GetPin(const char *name)
IOSpecialReg * pcmsk_reg
PCMSK IO register.
Provices flag and mask register for timer interrupts and connects irq lines to irqsystem.
HWTimer8_2C * timer0
timer 0 unit
IOReg< HWEeprom > eecr_reg
HWAdmux * admux
adc multiplexer unit
IOReg< HWTimerTinyX5 > tcnt_reg
counter register
void registerLine(int idx, IRQLine *irq)
AVR device class for ATTiny85, see AvrDevice_attinyX5.
#define AVR_REGISTER(name, class)
AVRDevice class for ATTiny25/45/85.
RWMemoryMember ** rw
The whole memory: R0-R31, IO, Internal RAM.
ADC type T25: ADC on attiny25/45/85.
IOReg< HWTimerTinyX5 > tocrc_reg
OCR register channel C.
IOReg< HWTimerTinyX5 > dt1b_reg
dead time generator register channel B
Provides the programming engine for flash self programming.
IOReg< HWTimerTinyX5 > dtps1_reg
dead time generator prescaler register
IOSpecialReg * gifr_reg
GIFR IO register.
IOReg< HWEeprom > eearl_reg
IOReg< HWTimer8 > ocra_reg
output compare A register
IOReg< HWTimerTinyX5 > tocra_reg
OCR register channel A.
RWSreg * statusRegister
the memory interface for status
Timer unit with 8Bit counter and 2 output compare unit.
IOReg< HWUSI_BR > usibr_reg
Pin-change interrupt on all pins of a port.
IRQLine * getLine(const std::string &name)
void SetTimerEventListener(TimerEventListener *listener)
Set event listener.
IOReg< HWTimerTinyX5 > dt1a_reg
dead time generator register channel A
FlashProgramming * spmRegister
CLKPRRegister * clkpr_reg
CLKPR IO register.
IOReg< HWTimerTinyX5 > tocrb_reg
OCR register channel B.
IOReg< HWTimer8 > ocrb_reg
output compare B register
IOSpecialReg timsk_reg
the TIMSKx register
Analog comparator peripheral.
IOReg< FlashProgramming > spmcr_reg
Implement OSCCAL register.
IOSpecialReg * gimsk_reg
GIMSK IO register.
External interrupt (INT0, INT1...) on a single pin, one and 2 bit configuration.
GPIORegister * gpior0_reg
GPIOR0 Register.