simulavr  1.1.0
Todo List
Class avr_op_SLEEP
SLEEP instruction not implemented
Class AvrDevice_at90canbase

This device isn't completely implemented. Some peripherals are not completed or missed.

Timer2 needs the external clocking bits

Class AvrDevice_atmega1284Abase
This device isn't completely implemented.
Class AvrDevice_atmega2560base
This device isn't completely implemented.
Class AvrDevice_atmega668base
This device isn't completely implemented. There is no boot loader section support for >= ATMega88, only normal interrupt vector start address supported, incomplete usart registers (and maybe more ...)
Class FlashProgramming
not implemented yet: SPM interrupt. Support of LPM operation. Setting boot lock bits. Read-While-Write, if run code in NRWW section.
Class HWPrescalerAsync
check external clock input and that TOSC1 and TOSC2 get back 0 if core read port input
Class HWUart
Needs rewrite! Only one async mode implemented!
Class IOSpecialReg
Set method could modify value, how to reflect it on TraceValue mechanism? Same problem for the get method.
Member Memory::GetAddressAtSymbol (const std::string &s)
if the symbol isn't found, it aborts with a message. Maybe it should raise a exeption to handle this on the caller side?
Class PrescalerMultiplexerT15
for the moment it's a placeholder, no multiplexing functionality
Class RWSreg
Replace the status register with an ordinary byte somewhere and simple inline access functions sN(), gN() to get/set flags. This should also make accesses faster.
Class Socket
The implementation of Socket has to be cleaned. In the moment, the Socket implementation for MingW acts only as client, the unix implementation could act also as server, but is this necessary?
Class SystemClock
In multiple core simulations which uses also gdb with single stepping we need a other solution to fit the time accurate behaviour. Currently on a single step from gdb the simulation runs until the command is completly executed which is NOT correct. Some commands need up to 4 cycles and the actual implementation do up to 4 steps for one step so the other cores run slower then in normal operation. This is not a problem today because we are not able to run multiple cores with gdb but this will be implementated later. So this version is only made for running the regression tests and stepping in gdb. Normal operation/simulation is not affected. (taken over from systemclock.cpp, but to check!)
Member SystemClock::Reschedule (SimulationMember *sm, SystemClockOffset newTime)
This method is possibly obsolete!