simulavr  1.1.0
decoder.cpp
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1 /*
2  ****************************************************************************
3  *
4  * simulavr - A simulator for the Atmel AVR family of microcontrollers.
5  * Copyright (C) 2001, 2002, 2003 Theodore A. Roth, Klaus Rudolph
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  ****************************************************************************
22  *
23  * $Id$
24  */
25 
26 #include "decoder.h"
27 #include "hwstack.h"
28 #include "flash.h"
29 #include "hwwado.h"
30 #include "hwsreg.h"
31 #include "avrerror.h"
32 #include "ioregs.h"
33 
34 static int n_bit_unsigned_to_signed(unsigned int val, int n );
35 
36 static int get_add_carry( byte res, byte rd, byte rr, int b );
37 static int get_add_overflow( byte res, byte rd, byte rr );
38 static int get_sub_carry( byte res, byte rd, byte rr, int b );
39 static int get_sub_overflow( byte res, byte rd, byte rr );
40 static int get_compare_carry( byte res, byte rd, byte rr, int b );
41 static int get_compare_overflow( byte res, byte rd, byte rr );
42 
45  mask_Rd_2 = 0x0030,
47  mask_Rd_3 = 0x0070,
49  mask_Rd_4 = 0x00f0,
51  mask_Rd_5 = 0x01f0,
52 
54  mask_Rr_3 = 0x0007,
56  mask_Rr_4 = 0x000f,
58  mask_Rr_5 = 0x020f,
59 
61  mask_K_8 = 0x0F0F,
63  mask_K_6 = 0x00CF,
64 
66  mask_k_7 = 0x03F8,
68  mask_k_12 = 0x0FFF,
70  mask_k_22 = 0x01F1,
71 
73  mask_reg_bit = 0x0007,
75  mask_sreg_bit = 0x0070,
77  mask_q_displ = 0x2C07,
78 
80  mask_A_5 = 0x00F8,
82  mask_A_6 = 0x060F
83 };
84 
85 static int get_rd_2( word opcode );
86 static int get_rd_3( word opcode );
87 static int get_rd_4( word opcode );
88 static int get_rd_5( word opcode );
89 static int get_rr_3( word opcode );
90 static int get_rr_4( word opcode );
91 static int get_rr_5( word opcode );
92 static byte get_K_8( word opcode );
93 static byte get_K_6( word opcode );
94 static int get_k_7( word opcode );
95 static int get_k_12( word opcode );
96 static int get_k_22( word opcode );
97 static int get_reg_bit( word opcode );
98 static int get_sreg_bit( word opcode );
99 static int get_q( word opcode );
100 static int get_A_5( word opcode );
101 static int get_A_6( word opcode );
102 
105  R1(get_rd_5(opcode)),
106  R2(get_rr_5(opcode)),
107  status(c->status) {}
108 
109 unsigned char avr_op_ADC::GetModifiedR() const {
110  return R1;
111 }
113  unsigned char rd = core->GetCoreReg(R1);
114  unsigned char rr = core->GetCoreReg(R2);
115  unsigned char res = rd + rr + status->C;
116 
117  status->H = get_add_carry(res, rd, rr, 3);
118  status->V = get_add_overflow(res, rd, rr);
119  status->N = (res >> 7) & 0x1;
120  status->S = status->N ^ status->V;
121  status->Z = (res & 0xff) == 0;
122  status->C = get_add_carry(res, rd, rr, 7);
123 
124  core->SetCoreReg(R1, res);
125 
126  return 1; //used clocks
127 }
128 
131  R1(get_rd_5(opcode)),
132  R2(get_rr_5(opcode)),
133  status(c->status) {}
134 
135 unsigned char avr_op_ADD::GetModifiedR() const {
136  return R1;
137 }
139  unsigned char rd = core->GetCoreReg(R1);
140  unsigned char rr = core->GetCoreReg(R2);
141  unsigned char res = rd + rr;
142 
143  status->H = get_add_carry(res, rd, rr, 3);
144  status->V = get_add_overflow(res, rd, rr);
145  status->N = (res >> 7) & 0x1;
146  status->S = status->N ^ status->V;
147  status->Z = (res & 0xff) == 0;
148  status->C = get_add_carry(res, rd, rr, 7);
149 
150  core->SetCoreReg(R1, res);
151 
152  return 1; //used clocks
153 }
154 
157  Rl(get_rd_2(opcode)),
158  Rh(get_rd_2(opcode) + 1),
159  K(get_K_6(opcode)),
160  status(c->status) {
161  }
162 
163 unsigned char avr_op_ADIW::GetModifiedR() const {
164  return Rl;
165 }
166 unsigned char avr_op_ADIW::GetModifiedRHi() const {
167  return Rh;
168 }
170  word rd = (core->GetCoreReg(Rh) << 8) + core->GetCoreReg(Rl);
171  word res = rd + K;
172  unsigned char rdh = core->GetCoreReg(Rh);
173 
174 
175  status->V = ~(rdh >> 7 & 0x1) & (res >> 15 & 0x1);
176  status->N = (res >> 15) & 0x1;
177  status->S = status->N ^ status->V;
178  status->Z = (res & 0xffff) == 0;
179  status->C = ~(res >> 15 & 0x1) & (rdh >> 7 & 0x1);
180 
181  core->SetCoreReg(Rl, res & 0xff);
182  core->SetCoreReg(Rh, res >> 8);
183 
184  return 2;
185 }
186 
189  R1(get_rd_5(opcode)),
190  R2(get_rr_5(opcode)),
191  status(c->status) {}
192 
194  unsigned char res = core->GetCoreReg(R1) & core->GetCoreReg(R2);
195 
196  status->V = 0;
197  status->N = (res >> 7) & 0x1;
198  status->S = status->N ^ status->V;
199  status->Z = (res & 0xff) == 0;
200 
201  core->SetCoreReg(R1, res);
202 
203  return 1;
204 }
205 
208  R1(get_rd_4(opcode)),
209  K(get_K_8(opcode)),
210  status(c->status) {}
211 
213  unsigned char rd = core->GetCoreReg(R1);
214  unsigned char res = rd & K;
215 
216  status->V = 0;
217  status->N = (res >> 7) & 0x1;
218  status->S = status->N ^ status->V;
219  status->Z = (res & 0xff) == 0;
220 
221  core->SetCoreReg(R1, res);
222 
223  return 1;
224 }
225 
228  R1(get_rd_5(opcode)),
229  status(c->status) {}
230 
232  unsigned char rd = core->GetCoreReg(R1);
233  unsigned char res = (rd >> 1) + (rd & 0x80);
234 
235  status->N = (res >> 7) & 0x1;
236  status->C = rd & 0x1;
237  status->V = status->N ^ status->C;
238  status->S = status->N ^ status->V;
239  status->Z = (res & 0xff) == 0;
240 
241  core->SetCoreReg(R1, res);
242 
243  return 1;
244 }
245 
246 
249  status(c->status),
250  Kbit(get_sreg_bit(opcode)) {}
251 
253  *status = (*status) & ~(1 << Kbit);
254 
255  return 1;
256 }
257 
260  R1(get_rd_5(opcode)),
261  Kbit(get_reg_bit(opcode)),
262  status(c->status) {}
263 
265  unsigned char rd = core->GetCoreReg(R1);
266  int T = status->T;
267  unsigned char res;
268 
269  if(T == 0)
270  res = rd & ~(1 << Kbit);
271  else
272  res = rd | (1 << Kbit);
273 
274  core->SetCoreReg(R1, res);
275 
276  return 1;
277 }
278 
281  status(c->status),
282  bitmask(1 << get_reg_bit(opcode)),
283  offset(n_bit_unsigned_to_signed(get_k_7(opcode), 7)) {}
284 
286  int clks;
287 
288  if((bitmask & (*(status))) == 0) {
289  core->DebugOnJump();
290  core->PC += offset;
291  clks = 2;
292  } else {
293  clks = 1;
294  }
295 
296  return clks;
297 }
298 
301  status(c->status),
302  bitmask(1 << get_reg_bit(opcode)),
303  offset(n_bit_unsigned_to_signed(get_k_7(opcode), 7)) {}
304 
306  int clks;
307 
308  if((bitmask & (*(status))) != 0) {
309  core->DebugOnJump();
310  core->PC += offset;
311  clks = 2;
312  } else {
313  clks = 1;
314  }
315 
316  return clks;
317 }
318 
321  status(c->status),
322  Kbit(get_sreg_bit(opcode)) {}
323 
325  *(status) = *(status) | 1 << Kbit;
326 
327  return 1;
328 }
329 
332  R1(get_rd_5(opcode)),
333  Kbit(get_reg_bit(opcode)),
334  status(c->status) {}
335 
337  status->T = ((core->GetCoreReg(R1) & (1 << Kbit)) != 0);
338 
339  return 1;
340 }
341 
343  DecodedInstruction(c, true),
344  KH(get_k_22(opcode)) {}
345 
347 {
348  word K_lsb = core->Flash->ReadMemWord((core->PC + 1) * 2);
349  int k = (KH << 16) + K_lsb;
350  int clkadd = core->flagXMega ? 1 : 2;
351 
353  core->stack->PushAddr(core->PC + 2);
354  core->DebugOnJump();
355  core->PC = k - 1;
356 
357  return core->PC_size + clkadd;
358 }
359 
362  ioreg(get_A_5(opcode)),
363  Kbit(get_reg_bit(opcode)) {}
364 
366  int clks = (core->flagXMega || core->flagTiny10) ? 1 : 2;
367 
369 
370  return clks;
371 }
372 
375  R1(get_rd_5(opcode)),
376  status(c->status) {}
377 
379  byte rd = core->GetCoreReg(R1);
380  byte res = 0xff - rd;
381 
382  status->N = (res >> 7) & 0x1;
383  status->C = 1;
384  status->V = 0;
385  status->S = status->N ^ status->V;
386  status->Z = (res & 0xff) == 0;
387 
388  core->SetCoreReg(R1, res);
389 
390  return 1;
391 }
392 
395  R1(get_rd_5(opcode)),
396  R2(get_rr_5(opcode)),
397  status(c->status) {}
398 
400  byte rd = core->GetCoreReg(R1);
401  byte rr = core->GetCoreReg(R2);
402  byte res = rd - rr;
403 
404  status->H = get_compare_carry(res, rd, rr, 3);
405  status->V = get_compare_overflow(res, rd, rr);
406  status->N = (res >> 7) & 0x1;
407  status->S = status->N ^ status->V;
408  status->Z = (res & 0xff) == 0;
409  status->C = get_compare_carry(res, rd, rr, 7);
410 
411  return 1;
412 }
413 
416  R1(get_rd_5(opcode)),
417  R2(get_rr_5(opcode)),
418  status(c->status) {}
419 
421  byte rd = core->GetCoreReg(R1);
422  byte rr = core->GetCoreReg(R2);
423  byte res = rd - rr - status->C;
424 
425  status->H = get_compare_carry(res, rd, rr, 3);
426  status->V = get_compare_overflow(res, rd, rr);
427  status->N = (res >> 7) & 0x1;
428  status->S = status->N ^ status->V;
429  status->C = get_compare_carry(res, rd, rr, 7);
430 
431  /* Previous value remains unchanged when result is 0; cleared otherwise */
432  bool Z = (res & 0xff) == 0;
433  bool prev_Z = status->Z;
434  status->Z = Z && prev_Z;
435 
436  return 1;
437 }
438 
439 
442  R1(get_rd_4(opcode)),
443  K(get_K_8(opcode)),
444  status(c->status) {}
445 
447  byte rd = core->GetCoreReg(R1);
448  byte res = rd - K;
449 
450  status->H = get_compare_carry(res, rd, K, 3);
451  status->V = get_compare_overflow(res, rd, K);
452  status->N = (res >> 7) & 0x1;
453  status->S = status->N ^ status->V;
454  status->Z = (res & 0xff) == 0;
455  status->C = get_compare_carry(res, rd, K, 7);
456 
457  return 1;
458 }
459 
462  R1(get_rd_5(opcode)),
463  R2(get_rr_5(opcode)),
464  status(c->status) {}
465 
467  int skip;
468  byte rd = core->GetCoreReg(R1);
469  byte rr = core->GetCoreReg(R2);
470  int clks;
471 
472  if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
473  skip = 3;
474  else
475  skip = 2;
476 
477  if(rd == rr) {
478  core->DebugOnJump();
479  core->PC += skip - 1;
480  clks = skip;
481  } else
482  clks = 1;
483 
484  return clks;
485 }
486 
489  R1(get_rd_5(opcode)),
490  status(c->status) {}
491 
493  byte res = core->GetCoreReg(R1) - 1;
494 
495  status->N = (res >> 7) & 0x1;
496  status->V = res == 0x7f;
497  status->S = status->N ^ status->V;
498  status->Z = (res & 0xff) == 0;
499 
500  core->SetCoreReg(R1, res);
501 
502  return 1;
503 }
504 
506  DecodedInstruction(c) {}
507 
509  unsigned new_PC = core->GetRegZ() + (core->eind->GetRegVal() << 16);
510 
512  core->stack->PushAddr(core->PC + 1);
513 
514  core->DebugOnJump();
515  core->PC = new_PC - 1;
516 
517  return core->flagXMega ? 3 : 4;
518 }
519 
521  DecodedInstruction(c) {}
522 
524  core->DebugOnJump();
525  core->PC = (core->eind->GetRegVal() << 16) + core->GetRegZ() - 1;
526 
527  return 2;
528 }
529 
532  R1(get_rd_5(opcode)) {}
533 
535  unsigned int Z;
536  unsigned char rampz = 0;
537 
538  if(core->rampz != NULL)
539  rampz = core->rampz->GetRegVal();
540  Z = (rampz << 16) + core->GetRegZ();
541 
542  core->SetCoreReg(R1, core->Flash->ReadMem(Z ^ 0x1));
543 
544  return 3;
545 }
546 
549  R1(get_rd_5(opcode)) {}
550 
552  unsigned int Z;
553  unsigned char rampz = 0;
554 
555  if(core->rampz != NULL)
556  rampz = core->rampz->GetRegVal();
557  Z = (rampz << 16) + core->GetRegZ();
558 
559  core->SetCoreReg(R1, core->Flash->ReadMem(Z ^ 0x1));
560 
561  /* post increment Z */
562  Z++;
563  if(core->rampz != NULL)
564  core->rampz->SetRegVal(Z >> 16);
565  core->SetCoreReg(30, Z & 0xff);
566  core->SetCoreReg(31, (Z >> 8) & 0xff);
567 
568  return 3;
569 }
570 
572  DecodedInstruction(c) {}
573 
575  unsigned char rampz = 0;
576 
577  if(core->rampz != NULL)
578  rampz = core->rampz->GetRegVal();
579  unsigned Z = (rampz << 16) + core->GetRegZ();
580 
581  core->SetCoreReg(0, core->Flash->ReadMem(Z ^ 0x1));
582 
583  return 3;
584 }
585 
588  R1(get_rd_5(opcode)),
589  R2(get_rr_5(opcode)),
590  status(c->status) {}
591 
593  byte rd = core->GetCoreReg(R1);
594  byte rr = core->GetCoreReg(R2);
595  byte res = rd ^ rr;
596 
597  status->V = 0;
598  status->N = (res >> 7) & 0x1;
599  status->S = status->N ^ status->V;
600  status->Z = (res & 0xff) == 0;
601 
602  core->SetCoreReg(R1, res);
603 
604  return 1;
605 }
606 
608  DecodedInstruction(c) {}
609 
611  unsigned char xaddr = 0;
612  int cycles = 1;
613  if(core->rampz != NULL)
614  xaddr = core->rampz->GetRegVal();
615  if(core->spmRegister != NULL) {
616  unsigned int Z = core->GetRegZ();
617  unsigned int D = core->GetCoreReg(0) + (core->GetCoreReg(1) << 8);
618  cycles += core->spmRegister->SPM_action(D, xaddr, Z);
619  // increment Z register
620  Z++;
621  core->SetCoreReg(30, Z & 0xff);
622  core->SetCoreReg(31, (Z >> 8) & 0xff);
623  if(core->rampz != NULL)
624  core->rampz->SetRegVal(Z >> 16);
625  }
626  return cycles;
627 }
628 
631  Rd(get_rd_3(opcode)),
632  Rr(get_rr_3(opcode)),
633  status(c->status) {}
634 
636  byte rd = core->GetCoreReg(Rd);
637  byte rr = core->GetCoreReg(Rr);
638 
639  word resp = rd * rr;
640  word res = resp << 1;
641 
642  status->Z = (res & 0xffff) == 0;
643  status->C= (resp >> 15) & 0x1;
644 
645  /* result goes in R1:R0 */
646  core->SetCoreReg(0, res & 0xff);
647  core->SetCoreReg(1, (res >> 8) & 0xff);
648 
649  return 2;
650 }
651 
652 
655  Rd(get_rd_3(opcode)),
656  Rr(get_rr_3(opcode)),
657  status(c->status) {}
658 
660  sbyte rd = core->GetCoreReg(Rd);
661  sbyte rr = core->GetCoreReg(Rr);
662 
663  word resp = rd * rr;
664  word res = resp << 1;
665 
666  status->Z = (res & 0xffff) == 0;
667  status->C = (resp >> 15) & 0x1;
668 
669  /* result goes in R1:R0 */
670  core->SetCoreReg(0, res & 0xff);
671  core->SetCoreReg(1, (res >> 8) & 0xff);
672 
673  return 2;
674 }
675 
676 
679  Rd(get_rd_3(opcode)),
680  Rr(get_rr_3(opcode)),
681  status(c->status) {}
682 
684  sbyte rd = core->GetCoreReg(Rd);
685  byte rr = core->GetCoreReg(Rr);
686 
687  word resp = rd * rr;
688  word res = resp << 1;
689 
690  status->Z = (res & 0xffff) == 0;
691  status->C = (resp >> 15) & 0x1;
692 
693  /* result goes in R1:R0 */
694  core->SetCoreReg(0, res & 0xff);
695  core->SetCoreReg(1, (res >> 8) & 0xff);
696  return 2;
697 }
698 
700  DecodedInstruction(c) {}
701 
703  unsigned int pc = core->PC;
704  /* Z is R31:R30 */
705  unsigned int new_pc = core->GetRegZ();
706 
708  core->stack->PushAddr(pc + 1);
709 
710  core->DebugOnJump();
711  core->PC = new_pc - 1;
712 
713  return core->PC_size + (core->flagXMega ? 0 : 1);
714 }
715 
717  DecodedInstruction(c) {}
718 
720  int new_pc = core->GetRegZ();
721 
722  core->DebugOnJump();
723  core->PC = new_pc - 1;
724 
725  return 2;
726 }
727 
730  R1(get_rd_5(opcode)),
731  ioreg(get_A_6(opcode)) {}
732 
735 
736  return 1;
737 }
738 
741  R1(get_rd_5(opcode)),
742  status(c->status) {}
743 
745  byte rd = core->GetCoreReg(R1);
746  byte res = rd + 1;
747 
748  status->N = (res >> 7) & 0x1;
749  status->V = rd == 0x7f;
750  status->S = status->N ^ status->V;
751  status->Z = (res & 0xff) == 0;
752 
753  core->SetCoreReg(R1, res);
754 
755  return 1;
756 }
757 
759  DecodedInstruction(c, true),
760  K(get_k_22(opcode)) {}
761 
763  word K_lsb = core->Flash->ReadMemWord((core->PC + 1) * 2);
764  core->DebugOnJump();
765  core->PC = (K << 16) + K_lsb - 1;
766  return 3;
767 }
768 
771  Rd(get_rd_5(opcode)),
772  K(get_q(opcode)) {}
773 
775  /* Y is R29:R28 */
776  word Y = core->GetRegY();
777 
778  core->SetCoreReg(Rd, core->GetRWMem(Y + K));
779 
780  return ((core->flagXMega || core->flagTiny10) && K == 0) ? 1 : 2;
781 }
782 
785  Rd(get_rd_5(opcode)),
786  K(get_q(opcode)) {}
787 
789  /* Z is R31:R30 */
790  word Z = core->GetRegZ();
791 
792  core->SetCoreReg(Rd, core->GetRWMem(Z + K));
793 
794  return ((core->flagXMega || core->flagTiny10) && K == 0) ? 1 : 2;
795 }
796 
799  R1(get_rd_4(opcode)),
800  K(get_K_8(opcode)) {}
801 
802 unsigned char avr_op_LDI::GetModifiedR() const {
803  return R1;
804 }
806  core->SetCoreReg(R1, K);
807 
808  return 1;
809 }
810 
812  DecodedInstruction(c, true),
813  R1(get_rd_5(opcode)) {}
814 
816  /* Get data at k in current data segment and put into Rd */
817  word offset = core->Flash->ReadMemWord((core->PC + 1) * 2);
818 
819  core->SetCoreReg(R1, core->GetRWMem(offset));
820  core->PC++;
821 
822  return 2;
823 }
824 
827  Rd(get_rd_5(opcode)) {}
828 
830  /* X is R27:R26 */
831  word X = core->GetRegX();
832 
833  core->SetCoreReg(Rd, core->GetRWMem(X));
834 
835  return (core->flagXMega || core->flagTiny10) ? 1 : 2;
836 }
837 
840  Rd(get_rd_5(opcode)) {}
841 
843  /* X is R27:R26 */
844  word X = core->GetRegX();
845  if (Rd == 26 || Rd == 27)
846  avr_error( "Result of operation is undefined" );
847 
848  /* Perform pre-decrement */
849  X--;
850  core->SetCoreReg(Rd, core->GetRWMem(X));
851  core->SetCoreReg(26, X & 0xff);
852  core->SetCoreReg(27, (X >> 8) & 0xff);
853 
854  return core->flagTiny10 ? 3 : 2;
855 }
856 
859  Rd(get_rd_5(opcode)) {}
860 
862  /* X is R27:R26 */
863  word X = core->GetRegX();
864  if (Rd == 26 || Rd == 27)
865  avr_error( "Result of operation is undefined" );
866 
867  /* Perform post-increment */
868  core->SetCoreReg(Rd, core->GetRWMem(X));
869  X++;
870  core->SetCoreReg(26, X & 0xff);
871  core->SetCoreReg(27, (X >> 8) & 0xff);
872 
873  return core->flagXMega ? 1 : 2;
874 }
875 
878  Rd(get_rd_5(opcode)) {}
879 
881  /* Y is R29:R28 */
882  word Y = core->GetRegY();
883  if (Rd == 28 || Rd == 29)
884  avr_error( "Result of operation is undefined" );
885 
886  /* Perform pre-decrement */
887  Y--;
888  core->SetCoreReg(Rd, core->GetRWMem(Y));
889  core->SetCoreReg(28, Y & 0xff);
890  core->SetCoreReg(29, (Y >> 8) & 0xff);
891 
892  return core->flagTiny10 ? 3 : 2;
893 }
894 
897  Rd(get_rd_5(opcode)) {}
898 
900  /* Y is R29:R28 */
901  word Y = core->GetRegY();
902  if (Rd == 28 || Rd == 29)
903  avr_error( "Result of operation is undefined" );
904 
905  /* Perform post-increment */
906  core->SetCoreReg(Rd, core->GetRWMem(Y));
907  Y++;
908  core->SetCoreReg(28, Y & 0xff);
909  core->SetCoreReg(29, (Y >> 8) & 0xff);
910 
911  return core->flagXMega ? 1 : 2;
912 }
913 
916  Rd(get_rd_5(opcode)) {}
917 
919  /* Z is R31:R30 */
920  word Z = core->GetRegZ();
921  if (Rd == 30 || Rd == 31)
922  avr_error( "Result of operation is undefined" );
923 
924  /* Perform post-increment */
925  core->SetCoreReg(Rd, core->GetRWMem(Z));
926  Z++;
927  core->SetCoreReg(30, Z & 0xff);
928  core->SetCoreReg(31, (Z >> 8) & 0xff);
929 
930  return core->flagXMega ? 1 : 2;
931 }
932 
935  Rd(get_rd_5(opcode)) {}
936 
938  /* Z is R31:R30 */
939  word Z = core->GetRegZ();
940  if (Rd == 30 || Rd == 31)
941  avr_error( "Result of operation is undefined" );
942 
943  /* Perform pre-decrement */
944  Z--;
945  core->SetCoreReg(Rd, core->GetRWMem(Z));
946  core->SetCoreReg(30, Z & 0xff);
947  core->SetCoreReg(31, (Z >> 8) & 0xff);
948 
949  return core->flagTiny10 ? 3 : 2;
950 }
951 
954  Rd(get_rd_5(opcode)) {}
955 
957  /* Z is R31:R30 */
958  word Z = core->GetRegZ();
959 
960  Z ^= 0x0001;
961  core->SetCoreReg(Rd , core->Flash->ReadMem(Z));
962 
963  return 3;
964 }
965 
967  DecodedInstruction(c) {}
968 
970  /* Z is R31:R30 */
971  word Z = core->GetRegZ();
972 
973  Z ^= 0x0001;
974  core->SetCoreReg(0 , core->Flash->ReadMem(Z));
975 
976  return 3;
977 }
978 
981  Rd(get_rd_5(opcode)) {}
982 
984  /* Z is R31:R30 */
985  word Z = core->GetRegZ();
986 
987  core->SetCoreReg(Rd , core->Flash->ReadMem(Z ^ 0x0001));
988 
989  Z++;
990  core->SetCoreReg(30, Z & 0xff);
991  core->SetCoreReg(31, (Z >> 8) & 0xff);
992 
993  return 3;
994 }
995 
998  Rd(get_rd_5(opcode)),
999  status(c->status) {}
1000 
1002  byte rd = core->GetCoreReg(Rd);
1003 
1004  byte res = (rd >> 1) & 0x7f;
1005 
1006  status->C = rd & 0x1;
1007  status->N = 0;
1008  status->V = status->N ^ status->C;
1009  status->S = status->N ^ status->V;
1010  status->Z = (res & 0xff) == 0;
1011 
1012  core->SetCoreReg(Rd, res);
1013 
1014  return 1;
1015 }
1016 
1018  DecodedInstruction(c),
1019  R1(get_rd_5(opcode)),
1020  R2(get_rr_5(opcode)) {}
1021 
1024  return 1;
1025 }
1026 
1028  DecodedInstruction(c),
1029  Rd((get_rd_4(opcode) - 16) << 1),
1030  Rs((get_rr_4(opcode) - 16) << 1) {}
1031 
1034  core->SetCoreReg(Rd + 1, core->GetCoreReg(Rs + 1));
1035 
1036  return 1;
1037 }
1038 
1040  DecodedInstruction(c),
1041  Rd(get_rd_5(opcode)),
1042  Rr(get_rr_5(opcode)),
1043  status(c->status) {}
1044 
1046  byte rd = core->GetCoreReg(Rd);
1047  byte rr = core->GetCoreReg(Rr);
1048 
1049  word res = rd * rr;
1050 
1051  status->Z = (res & 0xffff) == 0;
1052  status->C = (res >> 15) & 0x1;
1053 
1054  /* result goes in R1:R0 */
1055  core->SetCoreReg(0, res & 0xff);
1056  core->SetCoreReg(1, (res >> 8) & 0xff);
1057 
1058  return 2;
1059 }
1060 
1062  DecodedInstruction(c),
1063  Rd(get_rd_4(opcode)),
1064  Rr(get_rr_4(opcode)),
1065  status(c->status) {}
1066 
1068  sbyte rd = (sbyte)core->GetCoreReg(Rd);
1069  sbyte rr = (sbyte)core->GetCoreReg(Rr);
1070 
1071  sword res = rd * rr;
1072 
1073  status->Z = (res & 0xffff) == 0;
1074  status->C = (res >> 15) & 0x1;
1075 
1076  /* result goes in R1:R0 */
1077  core->SetCoreReg(0, res & 0xff);
1078  core->SetCoreReg(1, (res >> 8) & 0xff);
1079 
1080  return 2;
1081 }
1082 
1084  DecodedInstruction(c),
1085  Rd(get_rd_3(opcode)),
1086  Rr(get_rr_3(opcode)),
1087  status(c->status) {}
1088 
1090  sbyte rd = (sbyte)core->GetCoreReg(Rd);
1091  byte rr = core->GetCoreReg(Rr);
1092 
1093  sword res = rd * rr;
1094 
1095  status->Z = (res & 0xffff) == 0;
1096  status->C = (res >> 15) & 0x1;
1097 
1098 
1099  /* result goes in R1:R0 */
1100  core->SetCoreReg(0, res & 0xff);
1101  core->SetCoreReg(1, (res >> 8) & 0xff);
1102 
1103  return 2;
1104 }
1105 
1107  DecodedInstruction(c),
1108  Rd(get_rd_5(opcode)),
1109  status(c->status) {}
1110 
1112  byte rd = core->GetCoreReg(Rd);
1113  byte res = (0x0 - rd) & 0xff;
1114 
1115  status->H = ((res >> 3) | (rd >> 3)) & 0x1;
1116  status->V = res == 0x80;
1117  status->N = (res >> 7) & 0x1;
1118  status->S = status->N ^ status->V;
1119  status->Z = res == 0x0;
1120  status->C = res != 0x0;
1121 
1122  core->SetCoreReg(Rd, res);
1123 
1124  return 1;
1125 }
1126 
1128  DecodedInstruction(c) {}
1129 
1131  return 1;
1132 }
1133 
1135  DecodedInstruction(c),
1136  Rd(get_rd_5(opcode)),
1137  Rr(get_rr_5(opcode)),
1138  status(c->status) {}
1139 
1141  byte res = core->GetCoreReg(Rd) | core->GetCoreReg(Rr);
1142 
1143  status->V = 0;
1144  status->N = (res >> 7) & 0x1;
1145  status->S = status->N ^ status->V;
1146  status->Z = res == 0x0;
1147 
1148  core->SetCoreReg(Rd, res);
1149 
1150  return 1;
1151 }
1152 
1154  DecodedInstruction(c),
1155  R1(get_rd_4(opcode)),
1156  K(get_K_8(opcode)),
1157  status(c->status) {}
1158 
1160  byte res = core->GetCoreReg(R1) | K;
1161 
1162  status->V = 0;
1163  status->N = (res >> 7) & 0x1;
1164  status->S = status->N ^ status->V;
1165  status->Z = res == 0x0;
1166 
1167  core->SetCoreReg(R1, res);
1168 
1169  return 1;
1170 }
1171 
1173  DecodedInstruction(c),
1174  ioreg(get_A_6(opcode)),
1175  R1(get_rd_5(opcode)) {}
1176 
1179 
1180  return 1;
1181 }
1182 
1184  DecodedInstruction(c),
1185  R1(get_rd_5(opcode)) {}
1186 
1188  core->SetCoreReg(R1, core->stack->Pop());
1189 
1190  return 2;
1191 }
1192 
1194  DecodedInstruction(c),
1195  R1(get_rd_5(opcode)) {}
1196 
1199 
1200  return core->flagXMega ? 1 : 2;
1201 }
1202 
1204  DecodedInstruction(c),
1205  K(n_bit_unsigned_to_signed(get_k_12(opcode), 12)) {}
1206 
1208  core->stack->PushAddr(core->PC + 1);
1210  core->DebugOnJump();
1211  core->PC += K;
1212  core->PC &= (core->Flash->GetSize() - 1) >> 1;
1213 
1214  if(core->flagTiny10)
1215  return 4;
1216  return core->PC_size + (core->flagXMega ? 0 : 1);
1217 
1218 }
1219 
1221  DecodedInstruction(c) {}
1222 
1224  core->PC = core->stack->PopAddr() - 1;
1225 
1226  return core->PC_size + 2;
1227 }
1228 
1230  DecodedInstruction(c),
1231  status(c->status) {}
1232 
1234  core->PC = core->stack->PopAddr() - 1;
1235  status->I = 1;
1236 
1237  return core->PC_size + 2;
1238 }
1239 
1241  DecodedInstruction(c),
1242  K(n_bit_unsigned_to_signed(get_k_12(opcode), 12)) {}
1243 
1245  core->DebugOnJump();
1246  core->PC += K;
1247  core->PC &= (core->Flash->GetSize() - 1) >> 1;
1248 
1249  return 2;
1250 }
1251 
1253  DecodedInstruction(c),
1254  R1(get_rd_5(opcode)),
1255  status(c->status) {}
1256 
1258  byte rd = core->GetCoreReg(R1);
1259 
1260  byte res = (rd >> 1) | ((status->C << 7) & 0x80);
1261 
1262  status->C = rd & 0x1;
1263  status->N = (res >> 7) & 0x1;
1264  status->V = status->N ^ status->C;
1265  status->S = status->N ^ status->V;
1266  status->Z = res == 0;
1267 
1268  core->SetCoreReg(R1, res);
1269 
1270  return 1;
1271 }
1272 
1273 
1275  DecodedInstruction(c),
1276  R1(get_rd_5(opcode)),
1277  R2(get_rr_5(opcode)),
1278  status(c->status) {}
1279 
1280 unsigned char avr_op_SBC::GetModifiedR() const {
1281  return R1;
1282 }
1284  byte rd = core->GetCoreReg(R1);
1285  byte rr = core->GetCoreReg(R2);
1286 
1287  byte res = rd - rr - status->C;
1288 
1289  status->H = get_sub_carry(res, rd, rr, 3);
1290  status->V = get_sub_overflow(res, rd, rr);
1291  status->N = (res >> 7) & 0x1;
1292  status->S = status->N ^ status->V;
1293  status->C = get_sub_carry(res, rd, rr, 7);
1294 
1295  if((res & 0xff) != 0)
1296  status->Z = 0;
1297 
1298  core->SetCoreReg(R1, res);
1299 
1300  return 1;
1301 }
1302 
1304  DecodedInstruction(c),
1305  R1(get_rd_4(opcode)),
1306  K(get_K_8(opcode)),
1307  status(c->status) {}
1308 
1309 unsigned char avr_op_SBCI::GetModifiedR() const {
1310  return R1;
1311 }
1313  byte rd = core->GetCoreReg(R1);
1314 
1315  byte res = rd - K - status->C;
1316 
1317  status->H = get_sub_carry(res, rd, K, 3);
1318  status->V = get_sub_overflow(res, rd, K);
1319  status->N = (res >> 7) & 0x1;
1320  status->S = status->N ^ status->V;
1321  status->C = get_sub_carry(res, rd, K, 7);
1322 
1323  if((res & 0xff) != 0)
1324  status->Z = 0;
1325 
1326  core->SetCoreReg(R1, res);
1327 
1328  return 1;
1329 }
1330 
1332  DecodedInstruction(c),
1333  ioreg(get_A_5(opcode)),
1334  Kbit(get_reg_bit(opcode)) {}
1335 
1337  int clks = (core->flagXMega || core->flagTiny10) ? 1 : 2;
1338 
1340 
1341  return clks;
1342 }
1343 
1345  DecodedInstruction(c),
1346  ioreg(get_A_5(opcode)),
1347  Kbit(get_reg_bit(opcode)) {}
1348 
1350  int skip, clks;
1351 
1352  if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
1353  skip = 3;
1354  else
1355  skip = 2;
1356 
1357  if((core->GetIOReg(ioreg) & (1 << Kbit)) == 0) {
1358  core->DebugOnJump();
1359  core->PC += skip - 1;
1360  clks = skip;
1361  } else
1362  clks = 1;
1363 
1364  if(core->flagXMega)
1365  clks++;
1366 
1367  return clks;
1368 }
1369 
1371  DecodedInstruction(c),
1372  ioreg(get_A_5(opcode)),
1373  Kbit(get_reg_bit(opcode)) {}
1374 
1376  int skip, clks;
1377 
1378  if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
1379  skip = 3;
1380  else
1381  skip = 2;
1382 
1383  if((core->GetIOReg(ioreg) & (1 << Kbit)) != 0) {
1384  core->DebugOnJump();
1385  core->PC += skip - 1;
1386  clks = skip;
1387  } else
1388  clks = 1;
1389 
1390  if(core->flagXMega)
1391  clks++;
1392 
1393  return clks;
1394 }
1395 
1396 
1398  DecodedInstruction(c),
1399  R1(get_rd_2(opcode)),
1400  K(get_K_6(opcode)),
1401  status(c->status) {}
1402 
1403 unsigned char avr_op_SBIW::GetModifiedR() const {
1404  return R1;
1405 }
1406 unsigned char avr_op_SBIW::GetModifiedRHi() const {
1407  return R1 + 1;
1408 }
1410  byte rdl = core->GetCoreReg(R1);
1411  byte rdh = core->GetCoreReg(R1 + 1);
1412 
1413  word rd = (rdh << 8) + rdl;
1414  word res = rd - K;
1415 
1416  status->V = (rdh >> 7 & 0x1) & ~(res >> 15 & 0x1);
1417  status->N = (res >> 15) & 0x1;
1418  status->S = status->N ^ status->V;
1419  status->Z = (res & 0xffff) == 0;
1420  status->C = (res >> 15 & 0x1) & ~(rdh >> 7 & 0x1);
1421 
1422  core->SetCoreReg(R1, res & 0xff);
1423  core->SetCoreReg(R1 + 1, (res >> 8) & 0xff);
1424 
1425  return 2;
1426 }
1427 
1429  DecodedInstruction(c),
1430  R1(get_rd_5(opcode)),
1431  Kbit(get_reg_bit(opcode)) {}
1432 
1434  int skip, clks;
1435 
1436  if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
1437  skip = 3;
1438  else
1439  skip = 2;
1440 
1441  if((core->GetCoreReg(R1) & (1 << Kbit)) == 0) {
1442  core->DebugOnJump();
1443  core->PC += skip - 1;
1444  clks = skip;
1445  } else
1446  clks = 1;
1447 
1448  return clks;
1449 }
1450 
1452  DecodedInstruction(c),
1453  R1(get_rd_5(opcode)),
1454  Kbit(get_reg_bit(opcode)) {}
1455 
1457  int skip, clks;
1458 
1459  if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
1460  skip = 3;
1461  else
1462  skip = 2;
1463 
1464  if((core->GetCoreReg(R1) & (1 << Kbit)) != 0) {
1465  core->DebugOnJump();
1466  core->PC += skip - 1;
1467  clks = skip;
1468  } else
1469  clks = 1;
1470 
1471  return clks;
1472 }
1473 
1475  DecodedInstruction(c) {}
1476 
1478 #if 0 //TODO
1479  MCUCR *mcucr = (MCUCR *)avr_core_get_vdev_by_name( core, "MCUCR" );
1480 
1481  if (mcucr == NULL)
1482  avr_error( "MCUCR register not installed" );
1483 
1484  /* See if sleep mode is enabled */
1485  if ( mcucr_get_bit(mcucr, bit_SE) )
1486  {
1487  if ( mcucr_get_bit(mcucr, bit_SM) == 0 )
1488  {
1489  /* Idle Mode */
1490  avr_core_set_sleep_mode( core, SLEEP_MODE_IDLE);
1491  }
1492  else
1493  {
1494  /* Power Down Mode */
1495  avr_core_set_sleep_mode( core, SLEEP_MODE_PWR_DOWN);
1496  }
1497  }
1498 #endif
1499  return 1;
1500 }
1501 
1503  DecodedInstruction(c) {}
1504 
1506  unsigned char xaddr = 0;
1507  int cycles = 1;
1508  if(core->rampz != NULL)
1509  xaddr = core->rampz->GetRegVal();
1510  if(core->spmRegister != NULL) {
1511  unsigned int Z = core->GetRegZ();
1512  unsigned int D = core->GetCoreReg(0) + (core->GetCoreReg(1) << 8);
1513  cycles += core->spmRegister->SPM_action(D, xaddr, Z);
1514  }
1515  return cycles;
1516 }
1517 
1519  DecodedInstruction(c),
1520  R1(get_rd_5(opcode)),
1521  K(get_q(opcode)) {}
1522 
1524  /* Y is R29:R28 */
1525  unsigned int Y = core->GetRegY();
1526 
1527  core->SetRWMem(Y + K, core->GetCoreReg(R1));
1528 
1529  return (K == 0 && (core->flagXMega || core->flagTiny10)) ? 1 : 2;
1530 }
1531 
1533  DecodedInstruction(c),
1534  R1(get_rd_5(opcode)),
1535  K(get_q(opcode)) {}
1536 
1538  /* Z is R31:R30 */
1539  int Z = core->GetRegZ();
1540 
1541  core->SetRWMem(Z + K, core->GetCoreReg(R1));
1542 
1543  return (K == 0 && (core->flagXMega || core->flagTiny10)) ? 1 : 2;
1544 }
1545 
1547  DecodedInstruction(c, true),
1548  R1(get_rd_5(opcode)) {}
1549 
1551  /* Get data at k in current data segment and put into Rd */
1552  word k = core->Flash->ReadMemWord((core->PC + 1) * 2);
1553 
1554  core->SetRWMem(k, core->GetCoreReg(R1));
1555  core->PC++;
1556 
1557  return 2;
1558 }
1559 
1561  DecodedInstruction(c),
1562  R1(get_rd_5(opcode)) {}
1563 
1565  /* X is R27:R26 */
1566  word X = core->GetRegX();
1567 
1568  core->SetRWMem(X, core->GetCoreReg(R1));
1569 
1570  return (core->flagXMega || core->flagTiny10) ? 1 : 2;
1571 }
1572 
1574  DecodedInstruction(c),
1575  R1(get_rd_5(opcode)) {}
1576 
1578  /* X is R27:R26 */
1579  word X = core->GetRegX();
1580  if (R1 == 26 || R1 == 27)
1581  avr_error( "Result of operation is undefined" );
1582 
1583  /* Perform pre-decrement */
1584  X--;
1585  core->SetCoreReg(26, X & 0xff);
1586  core->SetCoreReg(27, (X >> 8) & 0xff);
1587  core->SetRWMem(X, core->GetCoreReg(R1));
1588 
1589  return 2;
1590 }
1591 
1593  DecodedInstruction(c),
1594  R1(get_rd_5(opcode)) {}
1595 
1597  /* X is R27:R26 */
1598  word X = core->GetRegX();
1599  if (R1 == 26 || R1 == 27)
1600  avr_error( "Result of operation is undefined" );
1601 
1602  core->SetRWMem(X, core->GetCoreReg(R1));
1603 
1604  /* Perform post-increment */
1605  X++;
1606  core->SetCoreReg(26, X & 0xff);
1607  core->SetCoreReg(27, (X >> 8) & 0xff);
1608 
1609  return (core->flagXMega || core->flagTiny10) ? 1 : 2;
1610 }
1611 
1613  DecodedInstruction(c),
1614  R1(get_rd_5(opcode)) {}
1615 
1617  /* Y is R29:R28 */
1618  word Y = core->GetRegY();
1619  if (R1 == 28 || R1 == 29)
1620  avr_error( "Result of operation is undefined" );
1621 
1622  /* Perform pre-decrement */
1623  Y--;
1624  core->SetCoreReg(28, Y & 0xff);
1625  core->SetCoreReg(29, (Y >> 8) & 0xff);
1626  core->SetRWMem(Y, core->GetCoreReg(R1));
1627 
1628  return 2;
1629 }
1630 
1632  DecodedInstruction(c),
1633  R1(get_rd_5(opcode)) {}
1634 
1636  /* Y is R29:R28 */
1637  word Y = core->GetRegY();
1638  if (R1 == 28 || R1 == 29)
1639  avr_error( "Result of operation is undefined" );
1640 
1641  core->SetRWMem(Y, core->GetCoreReg(R1));
1642 
1643  /* Perform post-increment */
1644  Y++;
1645  core->SetCoreReg(28, Y & 0xff);
1646  core->SetCoreReg(29, (Y >> 8) & 0xff);
1647 
1648  return (core->flagXMega || core->flagTiny10) ? 1 : 2;
1649 }
1650 
1652  DecodedInstruction(c),
1653  R1(get_rd_5(opcode)) {}
1654 
1656  /* Z is R31:R30 */
1657  word Z = core->GetRegZ();
1658  if (R1 == 30 || R1 == 31)
1659  avr_error( "Result of operation is undefined" );
1660 
1661  /* Perform pre-decrement */
1662  Z--;
1663  core->SetCoreReg(30, Z & 0xff);
1664  core->SetCoreReg(31, (Z >> 8) & 0xff);
1665  core->SetRWMem(Z, core->GetCoreReg(R1));
1666 
1667  return 2;
1668 }
1669 
1671  DecodedInstruction(c),
1672  R1(get_rd_5(opcode)) {}
1673 
1675  /* Z is R31:R30 */
1676  word Z = core->GetRegZ();
1677  if (R1 == 30 || R1 == 31)
1678  avr_error( "Result of operation is undefined" );
1679 
1680  core->SetRWMem(Z, core->GetCoreReg(R1));
1681 
1682  /* Perform post-increment */
1683  Z++;
1684  core->SetCoreReg(30, Z & 0xff);
1685  core->SetCoreReg(31, (Z >> 8) & 0xff);
1686 
1687  return (core->flagXMega || core->flagTiny10) ? 1 : 2;
1688 }
1689 
1691  DecodedInstruction(c),
1692  R1(get_rd_5(opcode)),
1693  R2(get_rr_5(opcode)),
1694  status(c->status) {}
1695 
1696 unsigned char avr_op_SUB::GetModifiedR() const {
1697  return R1;
1698 }
1700  byte rd = core->GetCoreReg(R1);
1701  byte rr = core->GetCoreReg(R2);
1702 
1703  byte res = rd - rr;
1704 
1705  status->H = get_sub_carry(res, rd, rr, 3);
1706  status->V = get_sub_overflow(res, rd, rr);
1707  status->N = (res >> 7) & 0x1;
1708  status->S = status->N ^ status->V;
1709  status->Z = (res & 0xff) == 0;
1710  status->C = get_sub_carry(res, rd, rr, 7);
1711 
1712  core->SetCoreReg(R1, res);
1713 
1714  return 1;
1715 }
1716 
1718  DecodedInstruction(c),
1719  R1(get_rd_4(opcode)),
1720  status(c->status),
1721  K(get_K_8(opcode)) {}
1722 
1723 unsigned char avr_op_SUBI::GetModifiedR() const {
1724  return R1;
1725 }
1727  byte rd = core->GetCoreReg(R1);
1728  byte res = rd - K;
1729 
1730  status->H = get_sub_carry(res, rd, K, 3);
1731  status->V = get_sub_overflow(res, rd, K);
1732  status->N = (res >> 7) & 0x1;
1733  status->S = status->N ^ status->V;
1734  status->Z = (res & 0xff) == 0;
1735  status->C = get_sub_carry(res, rd, K, 7);
1736 
1737  core->SetCoreReg(R1, res);
1738 
1739  return 1;
1740 }
1741 
1743  DecodedInstruction(c),
1744  R1(get_rd_5(opcode)) {}
1745 
1747  byte rd = core->GetCoreReg(R1);
1748  byte res = ((rd << 4) & 0xf0) | ((rd >> 4) & 0x0f);
1749 
1750  core->SetCoreReg(R1, res);
1751 
1752  return 1;
1753 }
1754 
1756  DecodedInstruction(c) {}
1757 
1759  if(core->wado != NULL)
1760  core->wado->Wdr();
1761 
1762  return 1;
1763 }
1764 
1766  DecodedInstruction(c) {}
1767 
1769  return BREAK_POINT+1;
1770 }
1771 
1773  DecodedInstruction(c) {}
1774 
1776  avr_error("Illegal opcode '%02x %02x' executed at PC=0x%x (%d)! Simulation terminated!",
1777  core->Flash->myMemory[core->PC*2+1], core->Flash->myMemory[core->PC*2], core->PC*2, core->PC);
1778  return 0;
1779 }
1780 
1781 static int get_add_carry( byte res, byte rd, byte rr, int b )
1782 {
1783  byte resb = res >> b & 0x1;
1784  byte rdb = rd >> b & 0x1;
1785  byte rrb = rr >> b & 0x1;
1786  return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
1787 }
1788 
1789 static int get_add_overflow( byte res, byte rd, byte rr )
1790 {
1791  byte res7 = res >> 7 & 0x1;
1792  byte rd7 = rd >> 7 & 0x1;
1793  byte rr7 = rr >> 7 & 0x1;
1794  return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
1795 }
1796 
1797 static int get_sub_carry( byte res, byte rd, byte rr, int b )
1798 {
1799  byte resb = res >> b & 0x1;
1800  byte rdb = rd >> b & 0x1;
1801  byte rrb = rr >> b & 0x1;
1802  return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
1803 }
1804 
1805 static int get_sub_overflow( byte res, byte rd, byte rr )
1806 {
1807  byte res7 = res >> 7 & 0x1;
1808  byte rd7 = rd >> 7 & 0x1;
1809  byte rr7 = rr >> 7 & 0x1;
1810  return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
1811 }
1812 
1813 static int get_compare_carry( byte res, byte rd, byte rr, int b )
1814 {
1815  byte resb = res >> b & 0x1;
1816  byte rdb = rd >> b & 0x1;
1817  byte rrb = rr >> b & 0x1;
1818  return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
1819 }
1820 
1821 static int get_compare_overflow( byte res, byte rd, byte rr )
1822 {
1823  byte res7 = res >> 7 & 0x1;
1824  byte rd7 = rd >> 7 & 0x1;
1825  byte rr7 = rr >> 7 & 0x1;
1826  /* The atmel data sheet says the second term is ~rd7 for CP
1827  * but that doesn't make any sense. You be the judge. */
1828  return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
1829 }
1830 static int n_bit_unsigned_to_signed( unsigned int val, int n )
1831 {
1832  /* Convert n-bit unsigned value to a signed value. */
1833  unsigned int mask;
1834 
1835  if ( (val & (1 << (n-1))) == 0)
1836  return (int)val;
1837 
1838  /* manually calculate two's complement */
1839  mask = (1 << n) - 1;
1840  return -1 * ((~val & mask) + 1);
1841 }
1842 
1843 /* Get register R24, 26, 28 or 30 - for ADIW and few other */
1844 static int get_rd_2( word opcode )
1845 {
1846  int reg = ((opcode & mask_Rd_2) >> 4) & 0x3;
1847  return (reg * 2) + 24;
1848 }
1849 
1850 static int get_rd_3( word opcode )
1851 {
1852  int reg = opcode & mask_Rd_3;
1853  return ((reg >> 4) & 0x7) + 16;
1854 }
1855 
1856 static int get_rd_4( word opcode )
1857 {
1858  int reg = opcode & mask_Rd_4;
1859  return ((reg >> 4) & 0xf) + 16;
1860 }
1861 
1862 static int get_rd_5( word opcode )
1863 {
1864  int reg = opcode & mask_Rd_5;
1865  return ((reg >> 4) & 0x1f);
1866 }
1867 
1868 static int get_rr_3( word opcode )
1869 {
1870  return (opcode & mask_Rr_3) + 16;
1871 }
1872 
1873 static int get_rr_4( word opcode )
1874 {
1875  return (opcode & mask_Rr_4) + 16;
1876 }
1877 
1878 static int get_rr_5( word opcode )
1879 {
1880  int reg = opcode & mask_Rr_5;
1881  return (reg & 0xf) + ((reg >> 5) & 0x10);
1882 }
1883 
1884 static byte get_K_8( word opcode )
1885 {
1886  int K = opcode & mask_K_8;
1887  return ((K >> 4) & 0xf0) + (K & 0xf);
1888 }
1889 
1890 static byte get_K_6( word opcode )
1891 {
1892  int K = opcode & mask_K_6;
1893  return ((K >> 2) & 0x0030) + (K & 0xf);
1894 }
1895 
1896 static int get_k_7( word opcode )
1897 {
1898  return (((opcode & mask_k_7) >> 3) & 0x7f);
1899 }
1900 
1901 static int get_k_12( word opcode )
1902 {
1903  return (opcode & mask_k_12);
1904 }
1905 
1906 static int get_k_22( word opcode )
1907 {
1908  /* Masks only the upper 6 bits of the address, the lower 16 bits
1909  * are in PC + 1.
1910  * Examples: "JMP 0xFFFF", "JMP 0x10FF" -> both have opcode: 0x940c
1911  * Examples: "JMP 0x1FFFF", "JMP 0x110FF" -> both have opcode: 0x940d
1912  */
1913  int k = opcode & mask_k_22;
1914  return ((k >> 3) & 0x003e) + (k & 0x1);
1915 }
1916 
1917 static int get_reg_bit( word opcode )
1918 {
1919  return opcode & mask_reg_bit;
1920 }
1921 
1922 static int get_sreg_bit( word opcode )
1923 {
1924  return (opcode & mask_sreg_bit) >> 4;
1925 }
1926 
1927 static int get_q( word opcode )
1928 {
1929  /* 00q0 qq00 0000 0qqq : Yuck! */
1930  int q = opcode & mask_q_displ;
1931  int qq = ( ((q >> 1) & 0x1000) + (q & 0x0c00) ) >> 7;
1932  return (qq & 0x0038) + (q & 0x7);
1933 }
1934 
1935 static int get_A_5( word opcode )
1936 {
1937  return (opcode & mask_A_5) >> 3;
1938 }
1939 
1940 static int get_A_6( word opcode )
1941 {
1942  int A = opcode & mask_A_6;
1943  return ((A >> 5) & 0x0030) + (A & 0xf);
1944 }
1945 
1946 
1947 
1948 
1950 {
1951  int decode;
1952 
1953  switch (opcode) {
1954  /* opcodes with no operands */
1955  case 0x9519:
1956  if(core->flagEIJMPInstructions)
1957  return new avr_op_EICALL(opcode, core); /* 1001 0101 0001 1001 | EICALL */
1958  else
1959  return new avr_op_ILLEGAL(opcode, core);
1960  case 0x9419:
1961  if(core->flagEIJMPInstructions)
1962  return new avr_op_EIJMP(opcode, core); /* 1001 0100 0001 1001 | EIJMP */
1963  else
1964  return new avr_op_ILLEGAL(opcode, core);
1965  case 0x95D8:
1966  if(core->flagELPMInstructions)
1967  return new avr_op_ELPM(opcode, core); /* 1001 0101 1101 1000 | ELPM */
1968  else
1969  return new avr_op_ILLEGAL(opcode, core);
1970  case 0x95F8:
1971  if(core->flagLPMInstructions)
1972  return new avr_op_ESPM(opcode, core); /* 1001 0101 1111 1000 | ESPM */
1973  else
1974  return new avr_op_ILLEGAL(opcode, core);
1975  case 0x9509:
1976  if(core->flagIJMPInstructions)
1977  return new avr_op_ICALL(opcode, core); /* 1001 0101 0000 1001 | ICALL */
1978  else
1979  return new avr_op_ILLEGAL(opcode, core);
1980  case 0x9409:
1981  if(core->flagIJMPInstructions)
1982  return new avr_op_IJMP(opcode, core); /* 1001 0100 0000 1001 | IJMP */
1983  else
1984  return new avr_op_ILLEGAL(opcode, core);
1985  case 0x95C8:
1986  if(!core->flagTiny10)
1987  /* except tiny10, all devices provide LPM instruction! */
1988  return new avr_op_LPM(opcode, core); /* 1001 0101 1100 1000 | LPM */
1989  else
1990  return new avr_op_ILLEGAL(opcode, core);
1991  case 0x0000: return new avr_op_NOP(opcode, core); /* 0000 0000 0000 0000 | NOP */
1992  case 0x9508: return new avr_op_RET(opcode, core); /* 1001 0101 0000 1000 | RET */
1993  case 0x9518: return new avr_op_RETI(opcode, core); /* 1001 0101 0001 1000 | RETI */
1994  case 0x9588: return new avr_op_SLEEP(opcode, core); /* 1001 0101 1000 1000 | SLEEP */
1995  case 0x95E8:
1996  if(core->flagLPMInstructions)
1997  return new avr_op_SPM(opcode, core); /* 1001 0101 1110 1000 | SPM */
1998  else
1999  return new avr_op_ILLEGAL(opcode, core);
2000  case 0x95A8: return new avr_op_WDR(opcode, core); /* 1001 0101 1010 1000 | WDR */
2001  case 0x9598: return new avr_op_BREAK(opcode, core); /* 1001 0101 1001 1000 | BREAK */
2002  default:
2003  {
2004  /* opcodes with two 5-bit register (Rd and Rr) operands */
2005  decode = opcode & ~(mask_Rd_5 | mask_Rr_5);
2006  switch ( decode ) {
2007  case 0x1C00: return new avr_op_ADC(opcode, core); /* 0001 11rd dddd rrrr | ADC or ROL */
2008  case 0x0C00: return new avr_op_ADD(opcode, core); /* 0000 11rd dddd rrrr | ADD or LSL */
2009  case 0x2000: return new avr_op_AND(opcode, core); /* 0010 00rd dddd rrrr | AND or TST */
2010  case 0x1400: return new avr_op_CP(opcode, core); /* 0001 01rd dddd rrrr | CP */
2011  case 0x0400: return new avr_op_CPC(opcode, core); /* 0000 01rd dddd rrrr | CPC */
2012  case 0x1000: return new avr_op_CPSE(opcode, core); /* 0001 00rd dddd rrrr | CPSE */
2013  case 0x2400: return new avr_op_EOR(opcode, core); /* 0010 01rd dddd rrrr | EOR or CLR */
2014  case 0x2C00: return new avr_op_MOV(opcode, core); /* 0010 11rd dddd rrrr | MOV */
2015  case 0x9C00:
2016  if(core->flagMULInstructions)
2017  return new avr_op_MUL(opcode, core); /* 1001 11rd dddd rrrr | MUL */
2018  else
2019  return new avr_op_ILLEGAL(opcode, core);
2020  case 0x2800: return new avr_op_OR(opcode, core); /* 0010 10rd dddd rrrr | OR */
2021  case 0x0800: return new avr_op_SBC(opcode, core); /* 0000 10rd dddd rrrr | SBC */
2022  case 0x1800: return new avr_op_SUB(opcode, core); /* 0001 10rd dddd rrrr | SUB */
2023  }
2024 
2025  /* opcode with a single register (Rd) as operand */
2026  decode = opcode & ~(mask_Rd_5);
2027  switch (decode) {
2028  case 0x9405: return new avr_op_ASR(opcode, core); /* 1001 010d dddd 0101 | ASR */
2029  case 0x9400: return new avr_op_COM(opcode, core); /* 1001 010d dddd 0000 | COM */
2030  case 0x940A: return new avr_op_DEC(opcode, core); /* 1001 010d dddd 1010 | DEC */
2031  case 0x9006:
2032  if(core->flagELPMInstructions)
2033  return new avr_op_ELPM_Z(opcode, core); /* 1001 000d dddd 0110 | ELPM */
2034  else
2035  return new avr_op_ILLEGAL(opcode, core);
2036  case 0x9007:
2037  if(core->flagELPMInstructions)
2038  return new avr_op_ELPM_Z_incr(opcode, core); /* 1001 000d dddd 0111 | ELPM */
2039  else
2040  return new avr_op_ILLEGAL(opcode, core);
2041  case 0x9403: return new avr_op_INC(opcode, core); /* 1001 010d dddd 0011 | INC */
2042  case 0x9000: return new avr_op_LDS(opcode, core); /* 1001 000d dddd 0000 | LDS */
2043  case 0x900C:
2044  if(!core->flagTiny1x)
2045  return new avr_op_LD_X(opcode, core); /* 1001 000d dddd 1100 | LD */
2046  else
2047  return new avr_op_ILLEGAL(opcode, core);
2048  case 0x900E:
2049  if(!core->flagTiny1x)
2050  return new avr_op_LD_X_decr(opcode, core); /* 1001 000d dddd 1110 | LD */
2051  else
2052  return new avr_op_ILLEGAL(opcode, core);
2053  case 0x900D:
2054  if(!core->flagTiny1x)
2055  return new avr_op_LD_X_incr(opcode, core); /* 1001 000d dddd 1101 | LD */
2056  else
2057  return new avr_op_ILLEGAL(opcode, core);
2058  case 0x8008:
2059  if(!core->flagTiny1x)
2060  return new avr_op_LDD_Y(opcode, core); /* 1000 000d dddd 1000 | LD */
2061  else
2062  return new avr_op_ILLEGAL(opcode, core);
2063  case 0x900A:
2064  if(!core->flagTiny1x)
2065  return new avr_op_LD_Y_decr(opcode, core); /* 1001 000d dddd 1010 | LD */
2066  else
2067  return new avr_op_ILLEGAL(opcode, core);
2068  case 0x9009:
2069  if(!core->flagTiny1x)
2070  return new avr_op_LD_Y_incr(opcode, core); /* 1001 000d dddd 1001 | LD */
2071  else
2072  return new avr_op_ILLEGAL(opcode, core);
2073  case 0x8000: return new avr_op_LDD_Z(opcode, core); /* 1000 000d dddd 0000 | LD */
2074  case 0x9002:
2075  if(!core->flagTiny1x)
2076  return new avr_op_LD_Z_decr(opcode, core); /* 1001 000d dddd 0010 | LD */
2077  else
2078  return new avr_op_ILLEGAL(opcode, core);
2079  case 0x9001:
2080  if(!core->flagTiny1x)
2081  return new avr_op_LD_Z_incr(opcode, core); /* 1001 000d dddd 0001 | LD */
2082  else
2083  return new avr_op_ILLEGAL(opcode, core);
2084  case 0x9004:
2085  if(core->flagLPMInstructions)
2086  return new avr_op_LPM_Z(opcode, core); /* 1001 000d dddd 0100 | LPM */
2087  else
2088  return new avr_op_ILLEGAL(opcode, core);
2089  case 0x9005:
2090  if(core->flagLPMInstructions)
2091  return new avr_op_LPM_Z_incr(opcode, core); /* 1001 000d dddd 0101 | LPM */
2092  else
2093  return new avr_op_ILLEGAL(opcode, core);
2094  case 0x9406: return new avr_op_LSR(opcode, core); /* 1001 010d dddd 0110 | LSR */
2095  case 0x9401: return new avr_op_NEG(opcode, core); /* 1001 010d dddd 0001 | NEG */
2096  case 0x900F:
2097  if(!core->flagTiny1x)
2098  return new avr_op_POP(opcode, core); /* 1001 000d dddd 1111 | POP */
2099  else
2100  return new avr_op_ILLEGAL(opcode, core);
2101  case 0x920F:
2102  if(!core->flagTiny1x)
2103  return new avr_op_PUSH(opcode, core); /* 1001 001d dddd 1111 | PUSH */
2104  else
2105  return new avr_op_ILLEGAL(opcode, core);
2106  case 0x9407: return new avr_op_ROR(opcode, core); /* 1001 010d dddd 0111 | ROR */
2107  case 0x9200: return new avr_op_STS(opcode, core); /* 1001 001d dddd 0000 | STS */
2108  case 0x920C:
2109  if(!core->flagTiny1x)
2110  return new avr_op_ST_X(opcode, core); /* 1001 001d dddd 1100 | ST */
2111  case 0x920E:
2112  if(!core->flagTiny1x)
2113  return new avr_op_ST_X_decr(opcode, core); /* 1001 001d dddd 1110 | ST */
2114  else
2115  return new avr_op_ILLEGAL(opcode, core);
2116  case 0x920D:
2117  if(!core->flagTiny1x)
2118  return new avr_op_ST_X_incr(opcode, core); /* 1001 001d dddd 1101 | ST */
2119  else
2120  return new avr_op_ILLEGAL(opcode, core);
2121  case 0x8208:
2122  if(!core->flagTiny1x)
2123  return new avr_op_STD_Y(opcode, core); /* 1000 001d dddd 1000 | ST */
2124  else
2125  return new avr_op_ILLEGAL(opcode, core);
2126  case 0x920A:
2127  if(!core->flagTiny1x)
2128  return new avr_op_ST_Y_decr(opcode, core); /* 1001 001d dddd 1010 | ST */
2129  else
2130  return new avr_op_ILLEGAL(opcode, core);
2131  case 0x9209:
2132  if(!core->flagTiny1x)
2133  return new avr_op_ST_Y_incr(opcode, core); /* 1001 001d dddd 1001 | ST */
2134  else
2135  return new avr_op_ILLEGAL(opcode, core);
2136  case 0x8200: return new avr_op_STD_Z(opcode, core); /* 1000 001d dddd 0000 | ST */
2137  case 0x9202:
2138  if(!core->flagTiny1x)
2139  return new avr_op_ST_Z_decr(opcode, core); /* 1001 001d dddd 0010 | ST */
2140  else
2141  return new avr_op_ILLEGAL(opcode, core);
2142  case 0x9201:
2143  if(!core->flagTiny1x)
2144  return new avr_op_ST_Z_incr(opcode, core); /* 1001 001d dddd 0001 | ST */
2145  else
2146  return new avr_op_ILLEGAL(opcode, core);
2147  case 0x9402: return new avr_op_SWAP(opcode, core); /* 1001 010d dddd 0010 | SWAP */
2148  }
2149 
2150  /* opcodes with a register (Rd) and a constant data (K) as operands */
2151  decode = opcode & ~(mask_Rd_4 | mask_K_8);
2152  switch ( decode ) {
2153  case 0x7000: return new avr_op_ANDI(opcode, core); /* 0111 KKKK dddd KKKK | CBR or ANDI */
2154  case 0x3000: return new avr_op_CPI(opcode, core); /* 0011 KKKK dddd KKKK | CPI */
2155  case 0xE000: return new avr_op_LDI(opcode, core); /* 1110 KKKK dddd KKKK | LDI or SER */
2156  case 0x6000: return new avr_op_ORI(opcode, core); /* 0110 KKKK dddd KKKK | SBR or ORI */
2157  case 0x4000: return new avr_op_SBCI(opcode, core); /* 0100 KKKK dddd KKKK | SBCI */
2158  case 0x5000: return new avr_op_SUBI(opcode, core); /* 0101 KKKK dddd KKKK | SUBI */
2159  }
2160 
2161  /* opcodes with a register (Rd) and a register bit number (b) as operands */
2162  decode = opcode & ~(mask_Rd_5 | mask_reg_bit);
2163  switch ( decode ) {
2164  case 0xF800: return new avr_op_BLD(opcode, core); /* 1111 100d dddd 0bbb | BLD */
2165  case 0xFA00: return new avr_op_BST(opcode, core); /* 1111 101d dddd 0bbb | BST */
2166  case 0xFC00: return new avr_op_SBRC(opcode, core); /* 1111 110d dddd 0bbb | SBRC */
2167  case 0xFE00: return new avr_op_SBRS(opcode, core); /* 1111 111d dddd 0bbb | SBRS */
2168  }
2169 
2170  /* opcodes with a relative 7-bit address (k) and a register bit number (b) as operands */
2171  decode = opcode & ~(mask_k_7 | mask_reg_bit);
2172  switch ( decode ) {
2173  case 0xF400: return new avr_op_BRBC(opcode, core); /* 1111 01kk kkkk kbbb | BRBC */
2174  case 0xF000: return new avr_op_BRBS(opcode, core); /* 1111 00kk kkkk kbbb | BRBS */
2175  }
2176 
2177  /* opcodes with a 6-bit address displacement (q) and a register (Rd) as operands */
2178  if(!core->flagTiny10 && !core->flagTiny1x) {
2179  decode = opcode & ~(mask_Rd_5 | mask_q_displ);
2180  switch ( decode ) {
2181  case 0x8008: return new avr_op_LDD_Y(opcode, core); /* 10q0 qq0d dddd 1qqq | LDD */
2182  case 0x8000: return new avr_op_LDD_Z(opcode, core); /* 10q0 qq0d dddd 0qqq | LDD */
2183  case 0x8208: return new avr_op_STD_Y(opcode, core); /* 10q0 qq1d dddd 1qqq | STD */
2184  case 0x8200: return new avr_op_STD_Z(opcode, core); /* 10q0 qq1d dddd 0qqq | STD */
2185  }
2186  }
2187 
2188  /* opcodes with a absolute 22-bit address (k) operand */
2189  decode = opcode & ~(mask_k_22);
2190  switch ( decode ) {
2191  case 0x940E:
2192  if(core->flagJMPInstructions)
2193  return new avr_op_CALL(opcode, core); /* 1001 010k kkkk 111k | CALL */
2194  else
2195  return new avr_op_ILLEGAL(opcode, core);
2196  case 0x940C:
2197  if(core->flagJMPInstructions)
2198  return new avr_op_JMP(opcode, core); /* 1001 010k kkkk 110k | JMP */
2199  else
2200  return new avr_op_ILLEGAL(opcode, core);
2201  }
2202 
2203  /* opcode with a sreg bit select (s) operand */
2204  decode = opcode & ~(mask_sreg_bit);
2205  switch ( decode ) {
2206  /* BCLR takes place of CL{C,Z,N,V,S,H,T,I} */
2207  /* BSET takes place of SE{C,Z,N,V,S,H,T,I} */
2208  case 0x9488: return new avr_op_BCLR(opcode, core); /* 1001 0100 1sss 1000 | BCLR */
2209  case 0x9408: return new avr_op_BSET(opcode, core); /* 1001 0100 0sss 1000 | BSET */
2210  }
2211 
2212  /* opcodes with a 6-bit constant (K) and a register (Rd) as operands */
2213  decode = opcode & ~(mask_K_6 | mask_Rd_2);
2214  switch ( decode ) {
2215  case 0x9600:
2216  if(core->flagIWInstructions)
2217  return new avr_op_ADIW(opcode, core); /* 1001 0110 KKdd KKKK | ADIW */
2218  else
2219  return new avr_op_ILLEGAL(opcode, core);
2220  case 0x9700:
2221  if(core->flagIWInstructions)
2222  return new avr_op_SBIW(opcode, core); /* 1001 0111 KKdd KKKK | SBIW */
2223  else
2224  return new avr_op_ILLEGAL(opcode, core);
2225  }
2226 
2227  /* opcodes with a 5-bit IO Addr (A) and register bit number (b) as operands */
2228  decode = opcode & ~(mask_A_5 | mask_reg_bit);
2229  switch ( decode ) {
2230  case 0x9800: return new avr_op_CBI(opcode, core); /* 1001 1000 AAAA Abbb | CBI */
2231  case 0x9A00: return new avr_op_SBI(opcode, core); /* 1001 1010 AAAA Abbb | SBI */
2232  case 0x9900: return new avr_op_SBIC(opcode, core); /* 1001 1001 AAAA Abbb | SBIC */
2233  case 0x9B00: return new avr_op_SBIS(opcode, core); /* 1001 1011 AAAA Abbb | SBIS */
2234  }
2235 
2236  /* opcodes with a 6-bit IO Addr (A) and register (Rd) as operands */
2237  decode = opcode & ~(mask_A_6 | mask_Rd_5);
2238  switch ( decode ) {
2239  case 0xB000: return new avr_op_IN(opcode, core); /* 1011 0AAd dddd AAAA | IN */
2240  case 0xB800: return new avr_op_OUT(opcode, core); /* 1011 1AAd dddd AAAA | OUT */
2241  }
2242 
2243  /* opcodes with a relative 12-bit address (k) operand */
2244  decode = opcode & ~(mask_k_12);
2245  switch ( decode ) {
2246  case 0xD000: return new avr_op_RCALL(opcode, core); /* 1101 kkkk kkkk kkkk | RCALL */
2247  case 0xC000: return new avr_op_RJMP(opcode, core); /* 1100 kkkk kkkk kkkk | RJMP */
2248  }
2249 
2250  /* opcodes with two 4-bit register (Rd and Rr) operands */
2251  decode = opcode & ~(mask_Rd_4 | mask_Rr_4);
2252  switch ( decode ) {
2253  case 0x0100:
2254  if(core->flagMOVWInstruction)
2255  return new avr_op_MOVW(opcode, core); /* 0000 0001 dddd rrrr | MOVW */
2256  else
2257  return new avr_op_ILLEGAL(opcode, core);
2258  case 0x0200:
2259  if(core->flagMULInstructions)
2260  return new avr_op_MULS(opcode, core); /* 0000 0010 dddd rrrr | MULS */
2261  else
2262  return new avr_op_ILLEGAL(opcode, core);
2263  }
2264 
2265  /* opcodes with two 3-bit register (Rd and Rr) operands */
2266  decode = opcode & ~(mask_Rd_3 | mask_Rr_3);
2267  switch ( decode ) {
2268  case 0x0300:
2269  if(core->flagMULInstructions)
2270  return new avr_op_MULSU(opcode, core); /* 0000 0011 0ddd 0rrr | MULSU */
2271  else
2272  return new avr_op_ILLEGAL(opcode, core);
2273  case 0x0308:
2274  if(core->flagMULInstructions)
2275  return new avr_op_FMUL(opcode, core); /* 0000 0011 0ddd 1rrr | FMUL */
2276  else
2277  return new avr_op_ILLEGAL(opcode, core);
2278  case 0x0380:
2279  if(core->flagMULInstructions)
2280  return new avr_op_FMULS(opcode, core); /* 0000 0011 1ddd 0rrr | FMULS */
2281  else
2282  return new avr_op_ILLEGAL(opcode, core);
2283  case 0x0388:
2284  if(core->flagMULInstructions)
2285  return new avr_op_FMULSU(opcode, core); /* 0000 0011 1ddd 1rrr | FMULSU */
2286  else
2287  return new avr_op_ILLEGAL(opcode, core);
2288  }
2289 
2290  } /* default */
2291  } /* first switch */
2292 
2293  //return NULL;
2294  return new avr_op_ILLEGAL(opcode, core);
2295 
2296 } /* decode opcode function */
2297 
int operator()()
Performs instruction.
Definition: decoder.cpp:420
AvrFlash * Flash
Definition: avrdevice.h:98
avr_op_CPC(word opcode, AvrDevice *c)
Definition: decoder.cpp:414
unsigned char R1
Definition: decoder.h:478
HWSreg * status
Definition: decoder.h:480
unsigned char ioreg
Definition: decoder.h:792
unsigned char ioreg
Definition: decoder.h:1617
Basic AVR device, contains the core functionality.
Definition: avrdevice.h:66
HWSreg * status
Definition: decoder.h:504
bool V
Definition: hwsreg.h:41
unsigned char Rs
Definition: decoder.h:1198
int operator()()
Performs instruction.
Definition: decoder.cpp:1596
int operator()()
Performs instruction.
Definition: decoder.cpp:956
HWSreg * status
Definition: decoder.h:688
unsigned char R1
Definition: decoder.h:410
int operator()()
Performs instruction.
Definition: decoder.cpp:788
avr_op_LPM(word opcode, AvrDevice *c)
Definition: decoder.cpp:966
int operator()()
Performs instruction.
Definition: decoder.cpp:1616
virtual unsigned char GetModifiedRHi() const
If this instruction modifies a pair of R0-R31 registers then ...
Definition: decoder.cpp:166
int operator()()
Performs instruction.
Definition: decoder.cpp:1505
int operator()()
Performs instruction.
Definition: decoder.cpp:1655
HWSreg * status
Definition: decoder.h:344
avr_op_BRBC(word opcode, AvrDevice *c)
Definition: decoder.cpp:279
int operator()()
Performs instruction.
Definition: decoder.cpp:880
unsigned char Kbit
Definition: decoder.h:1640
static int get_compare_carry(byte res, byte rd, byte rr, int b)
Definition: decoder.cpp:1813
avr_op_CBI(word opcode, AvrDevice *c)
Definition: decoder.cpp:360
avr_op_SPM(word opcode, AvrDevice *c)
Definition: decoder.cpp:1502
avr_op_ORI(word opcode, AvrDevice *c)
Definition: decoder.cpp:1153
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:1403
unsigned char * myMemory
Definition: memory.h:45
avr_op_ST_Z_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:1670
unsigned char Rl
Definition: decoder.h:125
int operator()()
Performs instruction.
Definition: decoder.cpp:1067
int operator()()
Performs instruction.
Definition: decoder.cpp:610
bool flagEIJMPInstructions
EICALL and EIJMP instructions are available (only on some devices with bigger flash) ...
Definition: avrdevice.h:118
int operator()()
Performs instruction.
Definition: decoder.cpp:574
avr_op_SBIW(word opcode, AvrDevice *c)
Definition: decoder.cpp:1397
int operator()()
Performs instruction.
Definition: decoder.cpp:1758
unsigned char Rr
Definition: decoder.h:687
unsigned char R2
Definition: decoder.h:433
unsigned char R1
Definition: decoder.h:1919
int operator()()
Performs instruction.
Definition: decoder.cpp:1177
int operator()()
Performs instruction.
Definition: decoder.cpp:1257
static int get_add_overflow(byte res, byte rd, byte rr)
Definition: decoder.cpp:1789
avr_op_SBI(word opcode, AvrDevice *c)
Definition: decoder.cpp:1331
avr_op_EIJMP(word opcode, AvrDevice *c)
Definition: decoder.cpp:520
avr_op_RCALL(word opcode, AvrDevice *c)
Definition: decoder.cpp:1203
avr_op_MUL(word opcode, AvrDevice *c)
Definition: decoder.cpp:1039
unsigned char ioreg
Definition: decoder.h:1639
unsigned char Kbit
Definition: decoder.h:1687
unsigned char R1
Definition: decoder.h:604
unsigned char Rd
Definition: decoder.h:965
unsigned char Rd
Definition: decoder.h:1008
int operator()()
Performs instruction.
Definition: decoder.cpp:252
AddressExtensionRegister * rampz
RAMPZ address extension register.
Definition: avrdevice.h:105
unsigned GetRegZ(void)
Get value of Z register (16bit)
Definition: avrdevice.cpp:503
unsigned char byte
Definition: types.h:26
int operator()()
Performs instruction.
Definition: decoder.cpp:774
int operator()()
Performs instruction.
Definition: decoder.cpp:1409
int operator()()
Performs instruction.
Definition: decoder.cpp:305
avr_op_BST(word opcode, AvrDevice *c)
Definition: decoder.cpp:330
unsigned char Kbit
Definition: decoder.h:1596
unsigned char R2
Definition: decoder.h:1548
HWSreg * status
Definition: decoder.h:1984
int operator()()
Performs instruction.
Definition: decoder.cpp:508
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:1723
HWSreg * status
Definition: decoder.h:100
unsigned char R1
Definition: decoder.h:342
avr_op_JMP(word opcode, AvrDevice *c)
Definition: decoder.cpp:758
HWSreg * status
Definition: decoder.h:320
avr_op_RETI(word opcode, AvrDevice *c)
Definition: decoder.cpp:1229
unsigned char Rr
Definition: decoder.h:1220
static int get_A_5(word opcode)
Definition: decoder.cpp:1935
unsigned char R1
Definition: decoder.h:502
avr_op_SLEEP(word opcode, AvrDevice *c)
Definition: decoder.cpp:1474
int operator()()
Performs instruction.
Definition: decoder.cpp:169
unsigned short word
Definition: types.h:27
avr_op_SBCI(word opcode, AvrDevice *c)
Definition: decoder.cpp:1303
avr_op_RJMP(word opcode, AvrDevice *c)
Definition: decoder.cpp:1240
unsigned char Rd
Definition: decoder.h:1291
unsigned char R2
Definition: decoder.h:1176
int operator()()
Performs instruction.
Definition: decoder.cpp:1477
int operator()()
Performs instruction.
Definition: decoder.cpp:138
avr_op_LDD_Y(word opcode, AvrDevice *c)
Definition: decoder.cpp:769
avr_op_INC(word opcode, AvrDevice *c)
Definition: decoder.cpp:739
int operator()()
Performs instruction.
Definition: decoder.cpp:492
avr_op_LDI(word opcode, AvrDevice *c)
Definition: decoder.cpp:797
unsigned int ReadMemWord(unsigned int addr)
Definition: flash.cpp:94
int operator()()
Performs instruction.
Definition: decoder.cpp:1233
unsigned char R1
Definition: decoder.h:1571
avr_op_COM(word opcode, AvrDevice *c)
Definition: decoder.cpp:373
unsigned char R1
Definition: decoder.h:1898
bool flagJMPInstructions
CALL and JMP instructions are available (only on devices with bigger flash)
Definition: avrdevice.h:116
unsigned char R2
Definition: decoder.h:152
HWSreg * status
Definition: decoder.h:1663
int operator()()
Performs instruction.
Definition: decoder.cpp:1111
unsigned char Rd
Definition: decoder.h:686
unsigned char ioreg
Definition: decoder.h:1378
avr_op_DEC(word opcode, AvrDevice *c)
Definition: decoder.cpp:487
unsigned char R1
Definition: decoder.h:1877
avr_op_ST_X_decr(word opcode, AvrDevice *c)
Definition: decoder.cpp:1573
HWSreg * status
Definition: decoder.h:389
HWSreg * status
Definition: decoder.h:1292
bool SetIORegBit(unsigned addr, unsigned bitaddr)
Set a bit value to lower IO register (without offset of 0x20!)
Definition: avrdevice.cpp:481
bool flagTiny10
core is a tiny4/5/9/10, change used clocks on some instructions and disables instructions ...
Definition: avrdevice.h:123
int operator()()
Performs instruction.
Definition: decoder.cpp:983
avr_op_ASR(word opcode, AvrDevice *c)
Definition: decoder.cpp:226
unsigned char K
Definition: decoder.h:1771
int operator()()
Performs instruction.
Definition: decoder.cpp:805
unsigned char ioreg
Definition: decoder.h:387
int operator()()
Performs instruction.
Definition: decoder.cpp:1699
unsigned char R1
Definition: decoder.h:241
avr_op_NEG(word opcode, AvrDevice *c)
Definition: decoder.cpp:1106
unsigned char R1
Definition: decoder.h:76
unsigned char R1
Definition: decoder.h:432
unsigned char R1
Definition: decoder.h:1175
bool SetRWMem(unsigned addr, unsigned char val)
Set a value to RW memory cell.
Definition: avrdevice.cpp:452
unsigned char R1
Definition: decoder.h:1770
unsigned char R1
Definition: decoder.h:174
int operator()()
Performs instruction.
Definition: decoder.cpp:1223
avr_op_SUBI(word opcode, AvrDevice *c)
Definition: decoder.cpp:1717
unsigned char R1
Definition: decoder.h:1355
HWSreg * status
Definition: decoder.h:1549
bool ClearIORegBit(unsigned addr, unsigned bitaddr)
Clear a bit value to lower IO register (without offset of 0x20!)
Definition: avrdevice.cpp:487
int operator()()
Performs instruction.
Definition: decoder.cpp:1349
HWSreg * status
Definition: decoder.h:1270
unsigned char Rd
Definition: decoder.h:944
avr_op_OR(word opcode, AvrDevice *c)
Definition: decoder.cpp:1134
avr_op_BRBS(word opcode, AvrDevice *c)
Definition: decoder.cpp:299
HWSreg * status
Definition: decoder.h:434
avr_op_AND(word opcode, AvrDevice *c)
Definition: decoder.cpp:187
int operator()()
Performs instruction.
Definition: decoder.cpp:1523
bool S
Definition: hwsreg.h:40
static int n_bit_unsigned_to_signed(unsigned int val, int n)
Definition: decoder.cpp:1830
HWSreg * status
Definition: decoder.h:814
avr_op_CPI(word opcode, AvrDevice *c)
Definition: decoder.cpp:440
int operator()()
Performs instruction.
Definition: decoder.cpp:466
HWSreg * status
Definition: decoder.h:2007
bool flagIJMPInstructions
ICALL and IJMP instructions are available (not on attiny1x devices)
Definition: avrdevice.h:117
bool flagLPMInstructions
LPM and SPM instructions are available (not on some tiny devices)
Definition: avrdevice.h:119
int operator()()
Performs instruction.
Definition: decoder.cpp:1635
static int get_sreg_bit(word opcode)
Definition: decoder.cpp:1922
int operator()()
Performs instruction.
Definition: decoder.cpp:1032
virtual void Push(unsigned char val)=0
Pushs one byte to stack.
unsigned char R1
Definition: decoder.h:1423
int operator()()
Performs instruction.
Definition: decoder.cpp:1244
avr_op_ADC(word opcode, AvrDevice *c)
Definition: decoder.cpp:103
unsigned char Kbit
Definition: decoder.h:321
HWSreg * status
Definition: decoder.h:269
int operator()()
Performs instruction.
Definition: decoder.cpp:1312
avr_op_ELPM_Z(word opcode, AvrDevice *c)
Definition: decoder.cpp:530
HWSreg * status
Definition: decoder.h:646
static int get_compare_overflow(byte res, byte rd, byte rr)
Definition: decoder.cpp:1821
static int get_rd_3(word opcode)
Definition: decoder.cpp:1850
unsigned char R2
Definition: decoder.h:99
int operator()()
Performs instruction.
Definition: decoder.cpp:1768
unsigned char R1
Definition: decoder.h:197
avr_op_SBRC(word opcode, AvrDevice *c)
Definition: decoder.cpp:1428
int operator()()
Performs instruction.
Definition: decoder.cpp:285
unsigned char Rd
Definition: decoder.h:1332
unsigned char Rd
Definition: decoder.h:1197
static byte get_K_6(word opcode)
Definition: decoder.cpp:1890
avr_op_PUSH(word opcode, AvrDevice *c)
Definition: decoder.cpp:1193
static int get_A_6(word opcode)
Definition: decoder.cpp:1940
signed char sbyte
Definition: types.h:28
int operator()()
Performs instruction.
Definition: decoder.cpp:1577
signed int K
Definition: decoder.h:1444
avr_op_NOP(word opcode, AvrDevice *c)
Definition: decoder.cpp:1127
unsigned char K
Definition: decoder.h:901
unsigned char Kbit
Definition: decoder.h:242
HWSreg * status
Definition: decoder.h:1244
unsigned char Kbit
Definition: decoder.h:388
HWSreg * status
Definition: decoder.h:411
int operator()()
Performs instruction.
Definition: decoder.cpp:523
unsigned char Rd
Definition: decoder.h:878
unsigned char R1
Definition: decoder.h:1982
avr_op_ESPM(word opcode, AvrDevice *c)
Definition: decoder.cpp:607
unsigned int K
Definition: decoder.h:835
avr_op_LD_X(word opcode, AvrDevice *c)
Definition: decoder.cpp:825
HWSreg * status
Definition: decoder.h:1573
int operator()()
Performs instruction.
Definition: decoder.cpp:592
unsigned char R2
Definition: decoder.h:1983
avr_op_FMUL(word opcode, AvrDevice *c)
Definition: decoder.cpp:629
HWSreg * status
Definition: decoder.h:128
unsigned char GetRegVal()
Definition: ioregs.h:42
avr_op_BLD(word opcode, AvrDevice *c)
Definition: decoder.cpp:258
unsigned char Rr
Definition: decoder.h:710
#define avr_error(...)
Definition: avrerror.h:135
int operator()()
Performs instruction.
Definition: decoder.cpp:1089
int operator()()
Performs instruction.
Definition: decoder.cpp:1726
unsigned char R2
Definition: decoder.h:456
avr_op_POP(word opcode, AvrDevice *c)
Definition: decoder.cpp:1183
const unsigned int PC_size
Definition: avrdevice.h:96
avr_op_SBRS(word opcode, AvrDevice *c)
Definition: decoder.cpp:1451
unsigned char K
Definition: decoder.h:127
unsigned char GetRWMem(unsigned addr)
Get a value of RW memory cell.
Definition: avrdevice.cpp:446
signed int K
Definition: decoder.h:1504
unsigned char Rd
Definition: decoder.h:1154
avr_op_OUT(word opcode, AvrDevice *c)
Definition: decoder.cpp:1172
avr_op_ST_Y_decr(word opcode, AvrDevice *c)
Definition: decoder.cpp:1612
HWSreg * status
Definition: decoder.h:1334
avr_op_RET(word opcode, AvrDevice *c)
Definition: decoder.cpp:1220
unsigned char K
Definition: decoder.h:2008
std::vector< DecodedInstruction * > DecodedMem
Definition: flash.h:42
int operator()()
Performs instruction.
Definition: decoder.cpp:683
static int get_rr_5(word opcode)
Definition: decoder.cpp:1878
int operator()()
Performs instruction.
Definition: decoder.cpp:1001
unsigned char R1
Definition: decoder.h:1547
signed char offset
Definition: decoder.h:271
unsigned char Rr
Definition: decoder.h:1269
bool SetIOReg(unsigned addr, unsigned char val)
Set a value to IO register (without offset of 0x20!)
Definition: avrdevice.cpp:475
avr_op_ST_Y_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:1631
unsigned char Rr
Definition: decoder.h:733
avr_op_ADD(word opcode, AvrDevice *c)
Definition: decoder.cpp:129
int operator()()
Performs instruction.
Definition: decoder.cpp:1746
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:1696
unsigned char Rd
Definition: decoder.h:1050
avr_op_EOR(word opcode, AvrDevice *c)
Definition: decoder.cpp:586
bool C
Definition: hwsreg.h:44
unsigned char Rd
Definition: decoder.h:1242
unsigned char R1
Definition: decoder.h:2006
HWSreg * status
Definition: decoder.h:734
int operator()()
Performs instruction.
Definition: decoder.cpp:815
int operator()()
Performs instruction.
Definition: decoder.cpp:365
avr_op_FMULS(word opcode, AvrDevice *c)
Definition: decoder.cpp:653
avr_op_ROR(word opcode, AvrDevice *c)
Definition: decoder.cpp:1252
avr_op_LPM_Z_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:979
int operator()()
Performs instruction.
Definition: decoder.cpp:231
HWSreg * status
Definition: decoder.h:711
unsigned char KH
Definition: decoder.h:366
unsigned char R1
Definition: decoder.h:151
avr_op_ADIW(word opcode, AvrDevice *c)
Definition: decoder.cpp:155
bool flagIWInstructions
ADIW and SBIW instructions are available (not on most tiny&#39;s!)
Definition: avrdevice.h:115
bool flagTiny1x
core is a tiny1x (but not tiny10!), change used clocks on some instructions and disables instructions...
Definition: avrdevice.h:124
avr_op_ANDI(word opcode, AvrDevice *c)
Definition: decoder.cpp:206
unsigned char K
Definition: decoder.h:1356
unsigned char Kbit
Definition: decoder.h:343
avr_op_EICALL(word opcode, AvrDevice *c)
Definition: decoder.cpp:505
bool flagMULInstructions
(F)MULxx instructions are available
Definition: avrdevice.h:121
int operator()()
Performs instruction.
Definition: decoder.cpp:1197
unsigned char R1
Definition: decoder.h:1792
unsigned char R1
Definition: decoder.h:98
avr_op_IJMP(word opcode, AvrDevice *c)
Definition: decoder.cpp:716
avr_op_SBC(word opcode, AvrDevice *c)
Definition: decoder.cpp:1274
unsigned char K
Definition: decoder.h:479
HWSreg * status
Definition: decoder.h:243
virtual void PushAddr(unsigned long addr)=0
Pushs a address to stack.
int operator()()
Performs instruction.
Definition: decoder.cpp:719
int operator()()
Performs instruction.
Definition: decoder.cpp:1283
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:802
int operator()()
Performs instruction.
Definition: decoder.cpp:1456
virtual unsigned char GetModifiedRHi() const
If this instruction modifies a pair of R0-R31 registers then ...
Definition: decoder.cpp:1406
unsigned GetRegX(void)
Get value of X register (16bit)
Definition: avrdevice.cpp:493
int operator()()
Performs instruction.
Definition: decoder.cpp:1433
unsigned char Rd
Definition: decoder.h:732
unsigned char K
Definition: decoder.h:1572
Base class of core instruction.
Definition: decoder.h:39
avr_op_ELPM_Z_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:547
bool Z
Definition: hwsreg.h:43
static int get_k_12(word opcode)
Definition: decoder.cpp:1901
unsigned char R2
Definition: decoder.h:645
int operator()()
Performs instruction.
Definition: decoder.cpp:937
unsigned int GetSize()
Definition: memory.h:85
unsigned char R1
Definition: decoder.h:1708
static int get_rr_3(word opcode)
Definition: decoder.cpp:1868
int operator()()
Performs instruction.
Definition: decoder.cpp:829
avr_op_LD_Y_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:895
avr_op_BSET(word opcode, AvrDevice *c)
Definition: decoder.cpp:319
avr_op_BCLR(word opcode, AvrDevice *c)
Definition: decoder.cpp:247
bool flagXMega
core is a XMEGA device, change used clocks on some instructions
Definition: avrdevice.h:125
bool I
Definition: hwsreg.h:37
unsigned char Rd
Definition: decoder.h:1133
unsigned char R1
Definition: decoder.h:1379
signed short sword
Definition: types.h:29
int operator()()
Performs instruction.
Definition: decoder.cpp:446
avr_op_CP(word opcode, AvrDevice *c)
Definition: decoder.cpp:393
HWSreg * status
Definition: decoder.h:1357
static int get_rr_4(word opcode)
Definition: decoder.cpp:1873
bool H
Definition: hwsreg.h:39
int operator()()
Performs instruction.
Definition: decoder.cpp:1022
static int get_reg_bit(word opcode)
Definition: decoder.cpp:1917
avr_op_FMULSU(word opcode, AvrDevice *c)
Definition: decoder.cpp:677
HWSreg * status
Definition: decoder.h:1221
decoder_operand_masks
Definition: decoder.cpp:43
avr_op_STD_Z(word opcode, AvrDevice *c)
Definition: decoder.cpp:1532
unsigned char R2
Definition: decoder.h:503
avr_op_LDD_Z(word opcode, AvrDevice *c)
Definition: decoder.cpp:783
int operator()()
Performs instruction.
Definition: decoder.cpp:336
HWSreg * status
Definition: decoder.h:153
int operator()()
Performs instruction.
Definition: decoder.cpp:1775
avr_op_ELPM(word opcode, AvrDevice *c)
Definition: decoder.cpp:571
unsigned char K
Definition: decoder.h:175
int operator()()
Performs instruction.
Definition: decoder.cpp:212
unsigned char R1
Definition: decoder.h:791
avr_op_SBIC(word opcode, AvrDevice *c)
Definition: decoder.cpp:1344
unsigned char GetIOReg(unsigned addr)
Get a value from IO register (without offset of 0x20!)
Definition: avrdevice.cpp:470
int operator()()
Performs instruction.
Definition: decoder.cpp:1564
int operator()()
Performs instruction.
Definition: decoder.cpp:1550
int operator()()
Performs instruction.
Definition: decoder.cpp:324
virtual unsigned char Pop()=0
Pops one byte from stack.
unsigned char R1
Definition: decoder.h:1661
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:1309
unsigned char R1
Definition: decoder.h:455
bool T
Definition: hwsreg.h:38
unsigned char Rd
Definition: decoder.h:986
avr_op_STS(word opcode, AvrDevice *c)
Definition: decoder.cpp:1546
int operator()()
Performs instruction.
Definition: decoder.cpp:659
unsigned GetRegY(void)
Get value of Y register (16bit)
Definition: avrdevice.cpp:498
unsigned char ReadMem(unsigned int addr)
Definition: flash.cpp:86
avr_op_BREAK(word opcode, AvrDevice *c)
Definition: decoder.cpp:1765
int operator()()
Performs instruction.
Definition: decoder.cpp:534
unsigned char R1
Definition: decoder.h:525
avr_op_MULSU(word opcode, AvrDevice *c)
Definition: decoder.cpp:1083
virtual unsigned long PopAddr()=0
Pops a address from stack.
int operator()()
Performs instruction.
Definition: decoder.cpp:1045
unsigned char bitmask
Definition: decoder.h:298
int operator()()
Performs instruction.
Definition: decoder.cpp:112
int operator()()
Performs instruction.
Definition: decoder.cpp:1674
static int get_add_carry(byte res, byte rd, byte rr, int b)
Definition: decoder.cpp:1781
unsigned char Rd
Definition: decoder.h:1029
avr_op_LSR(word opcode, AvrDevice *c)
Definition: decoder.cpp:996
avr_op_SUB(word opcode, AvrDevice *c)
Definition: decoder.cpp:1690
avr_op_LDS(word opcode, AvrDevice *c)
Definition: decoder.cpp:811
unsigned char R1
Definition: decoder.h:1961
avr_op_LD_X_decr(word opcode, AvrDevice *c)
Definition: decoder.cpp:838
static int get_rd_5(word opcode)
Definition: decoder.cpp:1862
unsigned char GetCoreReg(unsigned addr)
Get a value from core register.
Definition: avrdevice.cpp:459
unsigned char Kbit
Definition: decoder.h:220
unsigned char R1
Definition: decoder.h:583
HWSreg * status
Definition: decoder.h:198
unsigned char R1
Definition: decoder.h:1402
unsigned char R1
Definition: decoder.h:1814
avr_op_CPSE(word opcode, AvrDevice *c)
Definition: decoder.cpp:460
unsigned char K
Definition: decoder.h:1662
static int get_k_22(word opcode)
Definition: decoder.cpp:1906
int operator()()
Performs instruction.
Definition: decoder.cpp:1537
HWSreg * status
Definition: decoder.h:78
avr_op_ILLEGAL(word opcode, AvrDevice *c)
Definition: decoder.cpp:1772
unsigned char R2
Definition: decoder.h:77
HWSreg * status
Definition: decoder.h:1483
avr_op_LPM_Z(word opcode, AvrDevice *c)
Definition: decoder.cpp:952
int operator()()
Performs instruction.
Definition: decoder.cpp:899
DecodedInstruction * lookup_opcode(word opcode, AvrDevice *core)
Translates an opcode to a instance of DecodedInstruction.
Definition: decoder.cpp:1949
int operator()()
Performs instruction.
Definition: decoder.cpp:399
avr_op_SBIS(word opcode, AvrDevice *c)
Definition: decoder.cpp:1370
avr_op_LD_X_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:857
void OnCall()
Definition: hwstack.cpp:272
unsigned char bitmask
Definition: decoder.h:270
int operator()()
Performs instruction.
Definition: decoder.cpp:1336
unsigned char Kbit
Definition: decoder.h:1618
void Wdr()
Definition: hwwado.cpp:85
int SPM_action(unsigned int data, unsigned int xaddr, unsigned int addr)
Definition: flashprog.cpp:118
unsigned char R1
Definition: decoder.h:1835
bool SetCoreReg(unsigned addr, unsigned char val)
Set a value to core register.
Definition: avrdevice.cpp:464
avr_op_ICALL(word opcode, AvrDevice *c)
Definition: decoder.cpp:699
unsigned char Rd
Definition: decoder.h:1092
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:1280
avr_op_ST_Z_decr(word opcode, AvrDevice *c)
Definition: decoder.cpp:1651
static int get_rd_4(word opcode)
Definition: decoder.cpp:1856
unsigned char R1
Definition: decoder.h:1686
static int get_sub_carry(byte res, byte rd, byte rr, int b)
Definition: decoder.cpp:1797
static int get_sub_overflow(byte res, byte rd, byte rr)
Definition: decoder.cpp:1805
unsigned char R1
Definition: decoder.h:1525
bool N
Definition: hwsreg.h:42
HWSreg * status
Definition: decoder.h:526
avr_op_ST_X(word opcode, AvrDevice *c)
Definition: decoder.cpp:1560
int operator()()
Performs instruction.
Definition: decoder.cpp:918
unsigned char Rh
Definition: decoder.h:126
unsigned char K
Definition: decoder.h:857
unsigned char Rd
Definition: decoder.h:709
avr_op_LD_Z_decr(word opcode, AvrDevice *c)
Definition: decoder.cpp:933
int operator()()
Performs instruction.
Definition: decoder.cpp:744
int operator()()
Performs instruction.
Definition: decoder.cpp:346
avr_op_IN(word opcode, AvrDevice *c)
Definition: decoder.cpp:728
int operator()()
Performs instruction.
Definition: decoder.cpp:1159
unsigned char Rd
Definition: decoder.h:856
ThreadList m_ThreadList
Definition: hwstack.h:103
HWStack * stack
Definition: avrdevice.h:131
int operator()()
Performs instruction.
Definition: decoder.cpp:193
HWSreg * status
Definition: decoder.h:1155
unsigned char Kbit
Definition: decoder.h:1709
avr_op_WDR(word opcode, AvrDevice *c)
Definition: decoder.cpp:1755
static int get_k_7(word opcode)
Definition: decoder.cpp:1896
int operator()()
Performs instruction.
Definition: decoder.cpp:1207
static int get_rd_2(word opcode)
Definition: decoder.cpp:1844
unsigned char Rr
Definition: decoder.h:1333
HWSreg * status
Definition: decoder.h:1526
int operator()()
Performs instruction.
Definition: decoder.cpp:264
int operator()()
Performs instruction.
Definition: decoder.cpp:702
avr_op_LD_Y_decr(word opcode, AvrDevice *c)
Definition: decoder.cpp:876
signed char offset
Definition: decoder.h:299
avr_op_LD_Z_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:914
int operator()()
Performs instruction.
Definition: decoder.cpp:1130
avr_op_MULS(word opcode, AvrDevice *c)
Definition: decoder.cpp:1061
HWSreg * status
Definition: decoder.h:176
avr_op_ST_X_incr(word opcode, AvrDevice *c)
Definition: decoder.cpp:1592
int operator()()
Performs instruction.
Definition: decoder.cpp:551
unsigned int PC
Definition: avrdevice.h:93
avr_op_MOVW(word opcode, AvrDevice *c)
Definition: decoder.cpp:1027
HWSreg * status
Definition: decoder.h:457
unsigned char R1
Definition: decoder.h:1940
HWWado * wado
WDT timer.
Definition: avrdevice.h:134
int operator()()
Performs instruction.
Definition: decoder.cpp:378
AvrDevice * core
Link to device instance.
Definition: decoder.h:42
int operator()()
Performs instruction.
Definition: decoder.cpp:635
avr_op_CALL(word opcode, AvrDevice *c)
Definition: decoder.cpp:342
int operator()()
Performs instruction.
Definition: decoder.cpp:861
int operator()()
Performs instruction.
Definition: decoder.cpp:842
unsigned char R1
Definition: decoder.h:813
unsigned char K
Definition: decoder.h:1793
AddressExtensionRegister * eind
EIND address extension register.
Definition: avrdevice.h:106
FlashProgramming * spmRegister
Definition: avrdevice.h:99
bool flagMOVWInstruction
MOVW instruction is available.
Definition: avrdevice.h:122
unsigned char K
Definition: decoder.h:879
static int get_q(word opcode)
Definition: decoder.cpp:1927
int operator()()
Performs instruction.
Definition: decoder.cpp:733
unsigned char R1
Definition: decoder.h:1856
int operator()()
Performs instruction.
Definition: decoder.cpp:1375
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:163
static byte get_K_8(word opcode)
Definition: decoder.cpp:1884
void SetRegVal(unsigned char val)
Definition: ioregs.h:43
avr_op_SWAP(word opcode, AvrDevice *c)
Definition: decoder.cpp:1742
int operator()()
Performs instruction.
Definition: decoder.cpp:1140
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:109
unsigned char R1
Definition: decoder.h:2030
unsigned char ioreg
Definition: decoder.h:1595
unsigned char Rd
Definition: decoder.h:1219
unsigned char R1
Definition: decoder.h:644
int operator()()
Performs instruction.
Definition: decoder.cpp:762
virtual unsigned char GetModifiedR() const
If this instruction modifies a R0-R31 register then return its number, otherwise -1.
Definition: decoder.cpp:135
int operator()()
Performs instruction.
Definition: decoder.cpp:1187
int operator()()
Performs instruction.
Definition: decoder.cpp:969
unsigned char Rr
Definition: decoder.h:1243
avr_op_STD_Y(word opcode, AvrDevice *c)
Definition: decoder.cpp:1518
HWSreg * status
Definition: decoder.h:297
avr_op_MOV(word opcode, AvrDevice *c)
Definition: decoder.cpp:1017
unsigned char Rd
Definition: decoder.h:1268
HWSreg * status
Definition: decoder.h:219
#define BREAK_POINT
Definition: avrdevice.h:43
bool flagELPMInstructions
ELPM instructions are available (only on devices with bigger flash)
Definition: avrdevice.h:120
void DebugOnJump()
When a call/jump/cond-jump instruction was executed. For debugging.
Definition: avrdevice.cpp:437
unsigned char R1
Definition: decoder.h:900
unsigned char Rd
Definition: decoder.h:1071
unsigned char R1
Definition: decoder.h:923