36 #ifndef ATMEGA_256RFR2_H
37 #define ATMEGA_256RFR2_H (1)
51 #define RG_TRX_STATUS (0x1)
53 #define SR_CCA_DONE 0x1,0x80,7
55 #define SR_CCA_STATUS 0x1,0x40,6
57 #define SR_TRX_STATUS 0x1,0x1f,0
77 #define TRX_SLEEP (15)
80 #define BUSY_RX_AACK (17)
83 #define BUSY_TX_ARET (18)
86 #define RX_AACK_ON (22)
89 #define TX_ARET_ON (25)
92 #define RX_ON_NOCLK (28)
94 #ifndef RX_AACK_ON_NOCLK
95 #define RX_AACK_ON_NOCLK (29)
97 #ifndef BUSY_RX_AACK_NOCLK
98 #define BUSY_RX_AACK_NOCLK (30)
101 #define RG_TRX_STATE (0x2)
103 #define SR_TRAC_STATUS 0x2,0xe0,5
105 #define TRAC_SUCCESS (0)
107 #ifndef TRAC_SUCCESS_DATA_PENDING
108 #define TRAC_SUCCESS_DATA_PENDING (1)
110 #ifndef TRAC_SUCCESS_WAIT_FOR_ACK
111 #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
113 #ifndef TRAC_CHANNEL_ACCESS_FAILURE
114 #define TRAC_CHANNEL_ACCESS_FAILURE (3)
117 #define TRAC_NO_ACK (5)
120 #define TRAC_INVALID (7)
123 #define SR_TRX_CMD 0x2,0x1f,0
128 #define CMD_TX_START (2)
130 #ifndef CMD_FORCE_TRX_OFF
131 #define CMD_FORCE_TRX_OFF (3)
134 #define CMD_RX_ON (6)
137 #define CMD_TRX_OFF (8)
140 #define CMD_PLL_ON (9)
142 #ifndef CMD_RX_AACK_ON
143 #define CMD_RX_AACK_ON (22)
145 #ifndef CMD_TX_ARET_ON
146 #define CMD_TX_ARET_ON (25)
149 #define RG_TRX_CTRL_0 (0x3)
151 #define SR_PAD_IO 0x3,0xe0,5
153 #define SR_PAD_IO_CLKM 0x3,0x10,4
167 #define SR_CLKM_SHA_SEL 0x3,0x8,3
169 #define SR_CLKM_CTRL 0x3,0x7,0
170 #ifndef CLKM_no_clock
171 #define CLKM_no_clock (0)
174 #define CLKM_1MHz (1)
177 #define CLKM_2MHz (2)
180 #define CLKM_4MHz (3)
183 #define CLKM_8MHz (4)
186 #define CLKM_16MHz (5)
189 #define RG_TRX_CTRL_1 (0x4)
191 #define SR_PA_EXT_EN 0x4,0x80,7
193 #define SR_IRQ_2_EXT_EN 0x4,0x40,6
195 #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
197 #define SR_RX_BL_CTRL 0x4,0x10,4
199 #define SR_SPI_CMD_MODE 0x4,0xc,2
201 #define SR_IRQ_POLARITY 0x4,0x1,0
203 #define SR_IRQ_MASK_MODE 0x4,0x2,1
205 #define RG_PHY_TX_PWR (0x5)
207 #define SR_PA_BUF_LT 0x5,0xc0,6
209 #define SR_PA_LT 0x5,0x30,4
211 #define SR_TX_PWR 0x5,0xf,0
213 #define RG_PHY_RSSI (0x6)
215 #define SR_RX_CRC_VALID 0x6,0x80,7
217 #define SR_RND_VALUE 0x6,0x60,5
219 #define SR_RSSI 0x6,0x1f,0
221 #define RG_PHY_ED_LEVEL (0x7)
223 #define SR_ED_LEVEL 0x7,0xff,0
225 #define RG_PHY_CC_CCA (0x8)
227 #define SR_CCA_REQUEST 0x8,0x80,7
229 #define SR_CCA_MODE 0x8,0x60,5
231 #define SR_CHANNEL 0x8,0x1f,0
233 #define RG_CCA_THRES (0x9)
235 #define SR_CCA_ED_THRES 0x9,0xf,0
237 #define RG_RX_CTRL (0xa)
239 #define SR_PDT_THRES 0xa,0xf,0
241 #define RG_SFD_VALUE (0xb)
243 #define SR_SFD_VALUE 0xb,0xff,0
245 #define RG_TRX_CTRL_2 (0xc)
247 #define SR_RX_SAFE_MODE 0xc,0x80,7
249 #define SR_OQPSK_DATA_RATE 0xc,0x3,0
251 #define RG_ANT_DIV (0xd)
253 #define SR_ANT_SEL 0xd,0x80,7
255 #define SR_ANT_DIV_EN 0xd,0x8,3
257 #define SR_ANT_EXT_SW_EN 0xd,0x4,2
259 #define SR_ANT_CTRL 0xd,0x3,0
261 #define RG_IRQ_MASK (0xe)
263 #define SR_MASK_BAT_LOW 0xe,0x80,7
265 #define SR_MASK_TRX_UR 0xe,0x40,6
267 #define SR_MASK_AMI 0xe,0x20,5
269 #define SR_MASK_CCA_ED_READY 0xe,0x10,4
271 #define SR_MASK_TRX_END 0xe,0x8,3
273 #define SR_MASK_TRX_START 0xe,0x4,2
275 #define SR_MASK_PLL_LOCK 0xe,0x1,0
277 #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
279 #define RG_IRQ_STATUS (0xf)
281 #define SR_BAT_LOW 0xf,0x80,7
283 #define SR_TRX_UR 0xf,0x40,6
285 #define SR_AMI 0xf,0x20,5
287 #define SR_CCA_ED_READY 0xf,0x10,4
289 #define SR_RX_END 0xf,0x8,3
291 #define SR_RX_START 0xf,0x4,2
293 #define SR_PLL_LOCK 0xf,0x1,0
295 #define SR_PLL_UNLOCK 0xf,0x2,1
297 #define RG_VREG_CTRL (0x10)
299 #define SR_AVREG_EXT 0x10,0x80,7
301 #define SR_AVDD_OK 0x10,0x40,6
303 #define SR_DVREG_EXT 0x10,0x8,3
305 #define SR_DVDD_OK 0x10,0x4,2
307 #define RG_BATMON (0x11)
309 #define SR_BATMON_OK 0x11,0x20,5
311 #define SR_BATMON_HR 0x11,0x10,4
313 #define SR_BATMON_VTH 0x11,0xf,0
315 #define RG_XOSC_CTRL (0x12)
317 #define SR_XTAL_MODE 0x12,0xf0,4
319 #define SR_XTAL_TRIM 0x12,0xf,0
321 #define RG_RX_SYN (0x15)
323 #define SR_RX_PDT_DIS 0x15,0x80,7
325 #define SR_RX_PDT_LEVEL 0x15,0xf,0
327 #define RG_XAH_CTRL_1 (0x17)
329 #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
331 #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
333 #define SR_AACK_ACK_TIME 0x17,0x4,2
335 #define SR_AACK_PROM_MODE 0x17,0x2,1
337 #define RG_FTN_CTRL (0x18)
339 #define SR_FTN_START 0x18,0x80,7
341 #define RG_PLL_CF (0x1a)
343 #define SR_PLL_CF_START 0x1a,0x80,7
345 #define RG_PLL_DCU (0x1b)
347 #define SR_PLL_DCU_START 0x1b,0x80,7
349 #define RG_PART_NUM (0x1c)
351 #define SR_PART_NUM 0x1c,0xff,0
352 #ifndef RFR2_PART_NUM
353 #define RFR2_PART_NUM (148)
356 #define RG_VERSION_NUM (0x1d)
358 #define SR_VERSION_NUM 0x1d,0xff,0
359 #ifndef RFR2_VERSION_NUM_NONE
360 #define RFR2_VERSION_NUM_NONE (0)
362 #ifndef RFR2_VERSION_NUM_A
363 #define RFR2_VERSION_NUM_A (1)
366 #define RG_MAN_ID_0 (0x1e)
368 #define SR_MAN_ID_0 0x1e,0xff,0
370 #define RG_MAN_ID_1 (0x1f)
372 #define SR_MAN_ID_1 0x1f,0xff,0
374 #define RG_SHORT_ADDR_0 (0x20)
376 #define SR_SHORT_ADDR_0 0x20,0xff,0
378 #define RG_SHORT_ADDR_1 (0x21)
380 #define SR_SHORT_ADDR_1 0x21,0xff,0
382 #define RG_PAN_ID_0 (0x22)
384 #define SR_PAN_ID_0 0x22,0xff,0
386 #define RG_PAN_ID_1 (0x23)
388 #define SR_PAN_ID_1 0x23,0xff,0
390 #define RG_IEEE_ADDR_0 (0x24)
392 #define SR_IEEE_ADDR_0 0x24,0xff,0
394 #define RG_IEEE_ADDR_1 (0x25)
396 #define SR_IEEE_ADDR_1 0x25,0xff,0
398 #define RG_IEEE_ADDR_2 (0x26)
400 #define SR_IEEE_ADDR_2 0x26,0xff,0
402 #define RG_IEEE_ADDR_3 (0x27)
404 #define SR_IEEE_ADDR_3 0x27,0xff,0
406 #define RG_IEEE_ADDR_4 (0x28)
408 #define SR_IEEE_ADDR_4 0x28,0xff,0
410 #define RG_IEEE_ADDR_5 (0x29)
412 #define SR_IEEE_ADDR_5 0x29,0xff,0
414 #define RG_IEEE_ADDR_6 (0x2a)
416 #define SR_IEEE_ADDR_6 0x2a,0xff,0
418 #define RG_IEEE_ADDR_7 (0x2b)
420 #define SR_IEEE_ADDR_7 0x2b,0xff,0
422 #define RG_XAH_CTRL_0 (0x2c)
424 #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
426 #define SR_SLOTTED_OPERATION 0x2c,0x1,0
428 #define SR_MAX_CSMA_RETRES 0x2c,0xe,1
430 #define RG_CSMA_SEED_0 (0x2d)
432 #define SR_CSMA_SEED_0 0x2d,0xff,0
434 #define RG_CSMA_SEED_1 (0x2e)
436 #define SR_AACK_FVN_MODE 0x2e,0xc0,6
438 #define SR_AACK_SET_PD 0x2e,0x20,5
440 #define SR_AACK_DIS_ACK 0x2e,0x10,4
442 #define SR_AACK_I_AM_COORD 0x2e,0x8,3
444 #define SR_CSMA_SEED_1 0x2e,0x7,0
446 #define RG_CSMA_BE (0x2f)
448 #define SR_MAX_BE 0x2f,0xf0,4
450 #define SR_MIN_BE 0x2f,0xf,0
452 #define RADIO_NAME "ATmega256RFR2"
455 #define RADIO_PART_NUM (RFR2_PART_NUM)
458 # define RADIO_VERSION_NUM (RFR2_VERSION_NUM_A)
462 #define TRX_REGISTER_BASEADDR (0x140)
464 #define AES_REGISTER_BASEADDR (0x13c)
467 #define TRX_IF_RFA1 (1)
469 #define TRX_CMD_RADDR_MASK (0x3f)
472 #define TRX_RESET_TIME_US (6)
475 #define TRX_INIT_TIME_US (510)
478 #define TRX_PLL_LOCK_TIME_US (180)
482 #define TRX_CCA_TIME_US (140)
485 #define TRX_IRQ_PLL_LOCK _BV(0)
488 #define TRX_IRQ_PLL_UNLOCK _BV(1)
491 #define TRX_IRQ_RX_START _BV(2)
494 #define TRX_IRQ_RX_END _BV(3)
497 #define TRX_IRQ_CCA_ED _BV(4)
500 #define TRX_IRQ_AMI _BV(5)
503 #define TRX_IRQ_TX_END _BV(6)
506 #define TRX_MIN_CHANNEL (11)
509 #define TRX_MAX_CHANNEL (26)
512 #define TRX_NB_CHANNELS (16)
518 #define TRX_SUPPORTED_CHANNELS (0x7fff800UL)
520 #define TRX_SUPPORTS_BAND_2400 (1)
525 #define TRX_SUPPORTED_PAGES (42)
528 #define TRX_OQPSK250 (0)
531 #define TRX_OQPSK500 (1)
534 #define TRX_OQPSK1000 (2)
536 #define TRX_OQPSK2000 (3)
538 #define TRX_NONE (255)
544 extern volatile uint8_t SHADOW_IRQ_MASK;
545 static inline void disable_all_trx_irqs(
void)
547 SHADOW_IRQ_MASK = IRQ_MASK;
551 static inline void enable_all_trx_irqs(
void)
553 static bool already_shadowed = 0;
554 if (already_shadowed == 0)
557 SHADOW_IRQ_MASK = IRQ_MASK;
558 already_shadowed = 1;
565 SHADOW_IRQ_MASK = IRQ_MASK;
570 IRQ_MASK = SHADOW_IRQ_MASK;